Datasheet

LM49450
www.ti.com SNAS440D –FEBRUARY 2008–REVISED MAY 2013
Common Clock Settings for the DAC
In DAC_MODE 0, the DAC has an oversampling rate (OSR) of 125 but requires a 250xfs clock at point B. This
allows a simple clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or
USB) at 48kHz exactly. In the other DAC modes, the DAC requires a conventional 2^Nxfs clock for conversation.
The following table describes the clock required at point B for various clock sample rates in the different DAC
modes:
Table 5. Common DAC Clock Frequencies
Sample Rate Clock Required at B (MHz)
DAC MODE = 2b00 (OSR DAC MODE = 2b01 (OSR DAC MODE = 2b10 (OSR DAC MODE = 2b11 (OSR
= 125fs, Clock Required = = 128fs, Clock Required = = 64fs, Clock Required = = 32fs, Clock Required =
250fs) 256fs) 128fs) 128fs)
8 2 2.048 — —
11.025 2.75625 2.8224 — —
12 3 3.072 — —
16 4 4.096 — —
22.05 5.5125 5.6448 — —
24 6 6.144 — —
32 8 8.192 — —
44.1 11.025 11.2896 — —
48 — 12.288 — —
88.2 — — 11.2896 —
96 — — 12.288 —
176.4 — — — 22.5792
192 — — — 24.576
CHARGE PUMP CLOCK REGISTER (0x02h)
The charge pump clock register sets the charge pump frequency derived from MCLK when the LM49450 is in
DAC mode. Default value is for register 02h is 0x49h.
Table 6. Charge Pump Clock Register
Bit Name Value Description
B7 B6 B5 B4 B3 B2 B1 B0 Sets charge pump oscillator
CPDIV_7(B
frequency in DAC mode (derived
7)
from MCLK).
CPDIV_6
0 0 0 0 0 0 0 0 Bypass divider
(B6)
CPDIV_5
0 0 0 0 0 0 0 1 1
(B5)
0 0 0 0 0 0 1 0 1.5
CPDIV_4
(B4)
0 0 0 0 0 0 1 1 2
B7:B0
CPDIV_3
0 0 0 0 0 1 0 0 2.5
(B3)
0 0 0 0 0 1 0 1 3
CPDIV_2
(B2)
TO In 0.5 increments
CPDIV_1
1 1 1 1 1 1 0 1 127
(B1)
CPDIV_0
1 1 1 1 1 1 1 0 127.5
(B0)
1 1 1 1 1 1 1 1 128
CP_DIV REGISTER
LM49450 Clock Structure
This register is used to control the charge pump clock when the register field LINE_IN_ENABLE is low i.e. DAC
mode. When the register field LINE_IN_ENABLE is high, the Clocks module is held in reset and as a result no
CP_CLOCK_C is produced.
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