Datasheet

Clock

Decode

S Interface

Stereo DAC

MCLK

DAC_MODE[1:0] CP_CLOCK_C

ANALOG_CLOCK_C

S_CLK

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

www.ti.com

Table 3. Clock Control Register (continued)

Bit Name Value Description

B5 B4 B3 B2 B1 B0 Sets MCLK divider ratio

0 0 0 0 0 0 Bypass divider

0 0 0 0 0 1 1

0 0 0 0 1 0 1.5

RDIV_5 (B5)

RDIV_4 (B4)

0 0 0 0 1 1 2

RDIV_3 (B3)

B5:B0 0 0 0 1 0 0 2.5

RDIV_2 (B2)

0 0 0 1 0 1 5

RDIV_1 (B1)

RDIV_0 (B0)

TO In 0.5 increments

1 1 1 1 0 1 31

1 1 1 1 1 0 31.5

1 1 1 1 1 1 32

CLK NETWORK

Figure 72. CLK Network Diagram

LM49450 Clock Structure

The MCLK input is first divided by the R divider to product the clock at point B; this is then decoded according to

the DAC_MODE to produce a signal which goes to both the DAC digital and the I2S interface, and a signal which

goes to the DAC analog.

This table describes the relationship between the clocks, for each of the four possible DAC modes in terms of

audio input sampling frequency fs.

Table 4. Relationship between clocks for each of the four DAC modes

DAC MODE Description

OSR CLK at B DAC Digital CLK DAC Analog CLK

00 125 250fs 250fs 125fs

01 128 256fs 128fs 128fs

10 64 128fs 128fs 64fs

11 32 128fs 128fs 32fs

Product Folder Links: LM49450