Datasheet

LM49450
www.ti.com SNAS440D –FEBRUARY 2008–REVISED MAY 2013
Table 1. CONTROL REGISTERS — Register Map (continued)
Register Register B7 B6 B5 B4 B3 B2 B1 B0
Addess Name
0x0Ah CMP_0_MSB C0_15 C0_14 C0_13 C0_12 C0_111 C0_10 C0_09 C0_08
0x0Bh CMP_1_LSB C1_7 C1_6 C1_5 C1_4 C1_3 C1_2 C1_1 C1_0
0x0Ch CMP_1_MSB C1_15 C1_14 C1_13 C1_12 C1_11 C1_10 C1_09 C1_08
0x0Dh CMP_2_LSB C2_7 C2_6 C2_5 C2_4 C2_3 C2_2 C2_1 C2_0
0x0Eh CMP_2_MSB C2_15 C2_14 C2_13 C2_12 C2_11 C2_10 C2_09 C2_08
MODE CONTROL REGISTER (0x00h)
Default value is 0x00h.
Table 2. Mode Control Register
Bit Name Value Description
0 Internal reference selected
B7 EXT_REF
External reference selected. See External Reference
1
section.
B6 B5 Select DAC over sampling Rate
0 0 125
DAC_MODE_1 (B6)
B6:B5 0 1 128
DAC_MODE_0 (B5)
1 0 64
1 1 32
0 Default DAC compensation filter selected
B4 COMP
Programmable DAC compensation filter selected. See DAC
1
Compensation Filter section.
0 Fixed frequency oscillator selected
B3 SS
1 Spread spectrum oscillator selected
0 Un-mute device
B2 MUTE
1 Mute device
0 Device shutdown. Default state during a POR event
B0 ENABLE
1 Device enabled.
CLOCK CONTROL REGISTER (0x01h)
Default value is 0x00h.
Table 3. Clock Control Register
Bit Name Value Description
0 Default DAC state
B7 DAC_DITHER_OFF
1 Permanently disables DAC dither
0 Default DAC state
B6 DAC_DITHER_ON
1 Permanently enables DAC dither
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM49450