Datasheet

X X 23 22 012 X X 23 22 12 0
I2S_CLK
I2S_WS
I2S_DATA
LEFT CHANNEL DATA WORD RIGHT CHANNEL DATA WORD
23
22 21 20 012 X 23 21 20 012 X22 3
I2S_CLK
I2S_WS
I2S_DATA
LEFT CHANNEL DATA WORD RIGHT CHANNEL DATA WORD
X
23 22 21 01 X X 23 22 21 01 X
X
I2S_CLK
I2S_WS
I2S_DATA
LEFT CHANNEL DATA WORD RIGHT CHANNEL DATA WORD
LM49450
www.ti.com SNAS440D –FEBRUARY 2008–REVISED MAY 2013
Once the master device registers the ACK bit, the 8-bit register address word is sent. Each data bit should be
stable while SCL is HIGH. After the 8-bit register address is sent, the LM49450 sends another ACK bit. Following
the acknowledgement of the register address, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data is sent, the LM49450 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SDA is
high.
I
2
S DATA FORMAT
The LM49450 supports three I
2
S formats: Normal Mode (Figure 68), Left Justified Mode (Figure 69), and Right
Justified Mode (Figure 70). In Normal Mode, the audio data is transmitted MSB first, with the unused bits
following the LSB. In Left Justified Mode, the audio data format is similar to the Normal Mode, without the delay
between the LSB and the change in I
2
S_WS. In Right Justified Mode, the audio data MSB is transmitted after a
delay of a preset number of bits.
Figure 68. I
2
S Normal Input Format
Figure 69. I
2
S Left-Justified Input Format
Figure 70. I
2
S Right-Justified Input Format
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM49450