Datasheet

START MSB DEVICE ADDRESS
W
LSB
ACK
SCL
SDA
STOPMSB REGISTER ADDRESS LSB MSB REGISTER DATA LSB
ACK ACK
SDA
SCL
S
P
START condition
STOP condition
LM49450
SNAS440D –FEBRUARY 2008–REVISED MAY 2013 www.ti.com
APPLICATION INFORMATION
I
2
C-COMPATIBLE INTERFACE
The LM49450 is controlled through an I
2
C-compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open collector). The LM49450
and the master can communicate at clock rates up to 400kHz. Figure 65 shows the I
2
C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM49450 is a transmit/receive slave-
only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 66). Each data word, register address and register data,
transmitted over the bus is 8 bits long as is always followed by and acknowledge pulse (Figure 67). The
LM49450 device address is 1111101.
Figure 65. I
2
C Timing Diagram
Figure 66. START and STOP Diagram
Figure 67. Example I
2
C Write Cycle
BUS FORMAT
The I
2
C bus format is shown in Figure 69. The START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0
indicates the master is writing to the LM49450, R/W = 1 indicates the master wants to read data from the
LM49450). The data is latched in on the rising edge of the clock. Each address bit must be stable while SDA is
HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an
acknowledge clock pulse is generated by the slave device. If the LM49450 receives the correct address, the
device pulls the SDA line low, generating and acknowledge bit (ACK).
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