Datasheet
LM49370
www.ti.com
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
Electrical Characteristics
(1)(2)
(continued)
Unless otherwise stated PLL_V
DD
= 3.3V, D_V
DD
= 3.3V, BB_V
DD
= 1.8V, A_V
DD
= 3.3V, LS_V
DD
= 3.3V. The following
specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C.
LM49370
Symbol Parameter Conditions Units
Limit
(4)
Typical
(3)
(5)
CP_OUT AMPLIFIER
THD+N Total Harmonic Distortion + Noise V
O
= 1V
RMS
, 5kΩ load 0.02 %
C
BYPASS
= 1.0μF
PSRR Power Supply Rejection Ratio V
RIPPLE
= 200mVPP 86 dB
f
RIPPLE
= 217Hz
MONO ADC
R
ADC
ADC Ripple ±0.25 dB
ADC Passband Lower (HPF Mode 1), f
S
= 8 kHz 300 Hz
PB
ADC
Upper 3470 Hz
Above Passband 60 dB
SBA
ADC
ADC Stopband Attenuation
HPF Notch, 50 Hz/60 Hz (worst case) 58 dB
SNR
ADC
ADC Signal to Noise Ratio From CPI, A-weighted 90 dB
ADC
LEVEL
ADC Full Scale Input Level 1 V
RMS
STEREO DAC
R
DAC
DAC Ripple 0.1 dB
PB
DAC
DAC Passband 20 kHz
SBA
DAC
DAC Stopband Attenuation 70 dB
SNR
DAC
DAC Signal to Noise Ratio A-weighted, AUXOUT 85 dB
DR
DAC
DAC Dynamic Range 96 dB
DAC
LEVEL
DAC Full Scale Output Level 1 V
RMS
PLL
(8)
Min 0.5 MHz
F
IN
Input Frequency Range
Max 30 MHz
I2S/PCM
f
S
= 48kHz; 16 bit mode 1.536 MHz
f
S
= 48kHz; 25 bit mode 2.4 MHz
f
I2SCLK
I2S CLK Frequency
f
S
= 8kHz; 16 bit mode 0.256 MHz
f
S
= 8kHz; 25 bit mode 0.4 MHz
f
S
= 48kHz; 16 bit mode 0.768 MHz
f
S
= 48kHz; 25 bit mode 1.2 MHz
f
PCMCLK
PCM CLK Frequency
f
S
= 8kHz; 16 bit mode 0.128 MHz
f
S
= 8kHz; 25 bit mode 0.2 MHz
Min 40 % (min)
DC
I2S_CLK
I2S_CLK Duty Cycle
Max 60 % (max)
DC
I2S_WS
I2S_WS Duty Cycle 50 %
I2C
T
I2CSET
I2C Data Setup Time Refer to TRANSFERRING DATA for more
100 ns (min)
details
T
I2CHOLD
I2C Data Hold Time Refer to TRANSFERRING DATA for more
300 ns (min)
details
SPI
T
SPISETENB
Enable Setup Time 100 ns (min)
T
SPIHOLD-ENB
Enable Hold Time 100 ns (min)
T
SPISETD
Data Setup Time 100 ns (min)
(8) Disabling or bypassing the PLL will usually result in an improvement in noise measurements.
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