Datasheet
I
2
S
I
2
S_TX_SEL
I
2
S_SDO
I
2
S_SDI
Automatic Handshaking
Sample & Hold
PCM
PCM_TX_SEL
PCM_SDO
PCM_SDI
STEREO/
MONO
MONO_SUM_MODE
MONO_SUM_SEL
DAC_TX_SEL
@FSI
FIR
Interp
DSDM
DAC_SRC_MODE
Stereo DAC
IIR
Dec
Mono ADC
CIC
ADC_SRC_MODE
LM49370
www.ti.com
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
Figure 23. I
2
S to PCM Bridge
GPIO CONFIGURATION REGISTER
This register is used to control the GPIOs and to control the digital signal routing when using the ADC and DAC
to perform sample rate conversion.
Table 38. GPIO Control (0x1Fh)
Bits Field Description
2:0 GPIO_1_SEL This configures the GPIO_1 pin.
GPIO_1_SEL Does What? Direction
000
2
Disable HiZ
001
2
SPI_SDO Output
010
2
Output 0 Output
011
2
Output 1 Output
100
2
Read Input
101
2
Class D Enable Output
110
2
AUX Enable Output
111
2
Dig_Mic_Data Input
5:3 GPIO_2_SEL This configures the GPIO_2 pin.
GPIO_2_SEL Does What? Direction
000
2
Disable HiZ
001
2
SPI_SDO Output
010
2
Output 0 Output
011
2
Output 1 Output
100
2
Read Input
101
2
Class D Enable Output
110
2
Dig_Mic L Clock Output
111
2
Dig_Mic R Clock Output
6 ADC_SRC_MODE If set, the ADC analog is disabled and the digital is enabled, using the resampler input.
7 DAC_SRC_MODE This does not have to be set to use DAC in SRC mode, but should be set if the user wishes to disable the
DAC analog to save power.
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