Datasheet
PCM
CLKGEN
ADC_CLOCK
DAC_CLOCK
PCM_CLK_IN
PCM
SYNCGEN
PCM_SYNC_IN
PCM_SYNC
PCM_SYNC_OUT
PCM_CLOCK
PCM_CLK_OUT
LM49370
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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
Figure 22. PCM Audio Port CLOCK/SYNC Options
PCM PORT CLOCK CONFIGURATION REGISTER
This register is used to control the configuration of audio data interfaces.
Table 36. PCM Clock (0x1Dh)
Bits Field Description
3:0 PCM_CLOCK_ This programs a clock divider that divides the clock defined by PCM_CLOCK_SOURCE reg(0x1Ch).
GEN_MODE The divided clock is used to generate PCM_CLK in Master mode.
(1)
Value Divide By Ratio
0000
2
1
0001
2
2
0010
2
4
0011
2
6
0100
2
8
0101
2
10
0110
2
16
0111
2
20 —
1000
2
2.5 2/5
1001
2
3 1/3
1010
2
3.90625 32/125
1011
2
5 25/125
1100
2
7.8125 16/125
1101
2
— —
1110
2
— —
1111
2
— —
6:4 PCM_SYNC_MODE This programs a clock divider that divides PCM_CLK. The divided clock is used to generate
PCM_SYNC.
Valve Divide By
000
2
8
001
2
16
010
2
25
011
2
32
100
2
64
101
2
128
110
2
—
111
2
—
(1) For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a
divided by two version of the clock at the output of the R divider.
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