Datasheet

0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9

PCM_CLK

PCM_SDO/

PCM_SDI

PCM_SYNC

Short frame sync mode (PCM_SYNC_WIDTH = '00')

Long frame sync mode (PCM_SYNC_WIDTH = '11')

0 24 23 22 21 3 2 1 0 24 23 22 21 3 2 1 0 24

I2S_CLK

I2S_SDO/

I2S_SDI

I2S_WS

Left Word Right Word

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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Figure 20. I

S Serial Data Format (Left Justified)

Figure 21. PCM Serial Data Format (16 bit Slave Example)

PCM PORT MODE CONFIGURATION REGISTER

This register is used to control the audio data interfaces.

Table 35. PCM MODE (0x1Ch)

Bits Field Description

0 PCM_OUT_ENB If set, the PCM output bus is enabled. If this bit is cleared, thr PCM output will be tristate and all RX

clocks will be gated.

1 PCM_IN_ENB If set, the PCM input is enabled. If this bit is cleared, the PCM input is ignored and TX clocks are

generated.

3 PCM_CLOCK_SOURCE DAC or ADC Clock 0 = DAC, 1 = ADC

(1)

4 PCM_SYNC_MS If set, PCM_SYNC generation is enabled and is driven by the device (Master).

5 PCM_SDO_LSB_HZ If set, when the PCM port has run out of bits to transmit, it will tristate the SDO output.

6 PCM_COMPAND If set, the data sent to the PCM port is companded and the PCM data received by the PCM receiver

is treated as companded data.

7 PCM_ALAW_μLAW If PCM_ COMPAND is set, then the data across the PCM interface to the DAC and from the ADC is

companded as follows:

PCM_ALAW_μLAW Commanding Type

0 μ-LAW

1 A-Law

(1) For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a

divided by two version of the clock at the output of the R divider.

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