Datasheet
0 24 23 22 21 3 2 1 0 24 23 22 21 3 2 1 0 24
I2S_CLK
I2S_SDO/
I2S_SDI
I2S_WS
Left Word Right Word
LM49370
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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
Table 34. I2S Clock (0x1Bh) (continued)
Bit Field Description
s
5:2 I2S_CLOCK_GEN_MODE This programs a clock divider that divides the clock defined by I2S_CLOCK_SOURCE. This divided
clock is used to generate I2S_CLK in Master mode.
(1)
Value Divide By Ratio
0000
2
1
0001
2
2
0010
2
4
0011
2
6
0100
2
8
0101
2
10
0110
2
16
0111
2
20 —
1000
2
2.5 2/5
1001
2
3 1/3
1010
2
3.90625 32/125
1011
2
5 25/125
1100
2
7.8125 16/125
1101
2
— —
1110
2
— —
1111
2
— —
7:6 PCM_SYNC_WIDTH This programs the width of the PCM sync signal.
Generated SYNC Looks like:
00
2
1 bit (Used for Short PCM Modes)
01
2
4 bits (Used for Long PCM Modes)
10
2
8 bits (Used for Long PCM Modes)
11
2
15 bits (Used for Long PCM Modes)
Should not be set if the bits/word is less than 16.
(1) For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a
divided by two version of the clock at the output of the R divider.
DIGITAL AUDIO DATA FORMATS
I
2
S master mode can only be used when the DAC is enabled unless the FORCE_RQ bit is set. PCM Master
mode can only be used when the ADC is enabled, unless the FORCE_RQ bit is set. If the PCM receiver
interface is operated in slave mode the clock and sync should be enabled at the same time because the PCM
receiver uses the first PCM frame to calculate the PCM interface format. This format can not be changed unless
a soft reset is issued. Operating the LM49370 in master mode eliminates the risk of sample rate mismatch
between the data converters and the audio interfaces.
In slave mode, the PCM and I
2
S receivers only record the 1st 16 and 18 bits of the serial words respectively. The
I
2
S and PCM formats are as followed:
Figure 19. I
2
S Serial Data Format (Default Mode)
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