Datasheet

I2S
CLKGEN
ADC_CLOCK
DAC_CLOCK
I2S_CLK_IN
I2S
WSGEN
I2S_WS_IN
I2S_WS
I2S_WS_OUT
I2S_CLK
I2S_CLK_OUT
LM49370
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012 www.ti.com
I2S PORT MODE CONFIGURATION REGISTER
This register is used to control the audio data interfaces.
Table 33. I2S Mode (0x1Ah)
Bit Field Description
s
0 I2S_OUT_ENB If set, the I
2
S output bus is enabled. If cleared, the I
2
S output will be tristate and all RX clocks will be
gated.
1 I2S_IN_ENB If set, the I
2
S input is enabled. If this bit cleared, the I
2
S input is ignored and all TX clocks gated.
2 I2S_MODE This programs the format of the I
2
S interface.
Definition
0 Normal
1 Left Justified
3 I2S_STEREO_REVERSE If set, the left and right channels are reversed.
Operation
0 Normal
1 Reversed
4 I2S_WS_MS If set, I2S_WS generation is enabled and is Master. If cleared, I2S_WS acts as slave.
6:5 I2S_WS_GEN_MODE This programs the I
2
S word length.
Bits/Word
00
2
16
01
2
25
10
2
32
11
2
—
7 I2S_WORD_ORDER This bit alters the RX phasing of left and right channels. If this bit is cleared: right then left. If this bit is
set: left then right.
Figure 18. I2S Audio Port CLOCK/SYNC Options
I2S PORT CLOCK CONFIGURATION REGISTER
This register is used to control the audio data interfaces.
Table 34. I2S Clock (0x1Bh)
Bit Field Description
s
0 I2S_CLOCK_MS If set, then I
2
S clock generation is enabled and is Master. If this bit is cleared, then the I
2
S clock is driven
by the device slave.
1 I2S_CLOCK_SOURCE This selects the source of the clock to be used by the I2S clock generator.
I2S_CLOCK_SOURCE Clock is source from
0 DAC (from R divider)
1 ADC (from Q divider)
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