Datasheet
LM49370
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
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Table 8. PLL_P (0x04h)
(1)
Bits Field Description
3:0 PLL_P This programs the PLL output divider as follows:
PLL_P Output Divider Value
0 No Divided Clock
1 1
2 1.5
3 2
4 2.5
... 3 to 7
14 7.5
15 8
6:4 Q_DIV This programs the Q Divider
Q_DIV Divide Value
000
2
2
001
2
3
010
2
4
011
2
6
100
2
8
101
2
10
110
2
12
111
2
13
7 FAST_VCO This programs the PLL VCO range:
FAST_VCO PLL VCO Range
0 40 to 60MHz
1 60 to 80MHz
(1) See Further Notes on PLL Programming for more details.
The division of the P divider is derived from PLL_P such that:
P = (PLL_P + 1) / 2
PLL N MODULUS CONFIGURATION REGISTER
This register is used to control the modulation applied to the feedback divider of the PLL.
Table 9. PLL_N_MOD (0x05h)
(1)
Bits Field Description
4:0 PLL_N_MOD This programs the PLL N divider's fractional component:
PLL_N_MOD Fractional Addition
0 0/32
1 1/32
2 to 30 2/32 to 30/32
31 31/32
6:5 PLL_CLK_SEL This selects the clock to be used as input for the audio PLL.
PLL_INPUT_CLK
00
2
MCLK
01
2
I2S_CLK_IN
10
2
PCM_CLK_IN
11
2
—
7 RSVD Reserved.
(1) See Further Notes on PLL Programming for more details.
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