Datasheet

LM49370
www.ti.com SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
Methods for producing these clock frequencies are described in the PLL Section.
PLL M DIVIDER CONFIGURATION REGISTER
This register is used to control the input section of the PLL.
Table 6. PLL_M (0x02h)
(1)
Bits Field Description
0 RSVD RESERVED
6:0 PLL_M PLL_M Input Divider Value
0 No Divided Clock
1 1
2 1.5
3 2
4 2.5
... 3 to 63
126 63.5
127 64
7 FORCERQ If set, the R and Q divider are enabled and the DAC and ADC clocks are propagated. This allows operation of
the I
2
S and PCM interfaces without the ADC or DAC being enabled, for example to act as a bridge or a clock
master.
(1) See Further Notes on PLL Programming for more detail.
The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz.
The division of the M divider is derived from PLL_M such that:
M = (PLL_M + 1) / 2
PLL N DIVIDER CONFIGURATION REGISTER
This register is used to control the feedback divider of the PLL.
Table 7. PLL_N (0x03h)
(1)
Bits Field Description
7:0 PLL_N This programs the PLL feedback divider as follows:
PLL_N Feedback Divider Value
0 to 10 10
11 11
12 12
13 13
14 14
… …
249 249
250 to 255 250
(1) See Further Notes on PLL Programming for further details.
The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be
the target resting VCO frequency, F
VCO
. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz.
Fin/M is often referred to as F
comp
(comparison frequency) or F
ref
(reference frequency), in this document F
comp
is
used.
The integer division of the N divider is derived from PLL_N such that:
For 9 < PLL_N < 251: N = PLL_N
PLL P DIVIDER CONFIGURATION REGISTER
This register is used to control the output divider of the PLL.
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