Datasheet

MCLK
I2S_CLK
PCM_CLK
PCM Interface
I2S Interface
Stereo DAC
Mono ADC
PLL
% Q
% R
C
B
A
From on chip 12 MHz oscillator
USE_ONCHIP_OSC
(to DET, PMC)
LM49370
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012 www.ti.com
Figure 13. LM49370 Clock Network
COMMON CLOCK SETTINGS FOR THE DAC & ADC
When DAC_MODE = '00' (bits 7:6 of (0x00h)), the DAC has an over sampling ratio of 125 but requires a 250*fs
clock at point B. This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems
with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock required at point B for various
clock sample rates in the different DAC modes:
Table 4. Common DAC Clock Frequencies
DAC Sample Rate (kHz) Clock Required at B (OSR = 125) Clock Required at B (OSR = 128)
8 2 MHz 2.048 MHz
11.025 2.75625 MHz 2.8224 MHz
12 3 MHz 3.072 MHz
16 4 MHz 4.096 MHz
22.05 5.5125 MHz 5.6448 MHz
24 6 MHz 6.144 MHz
32 8 MHz 8.192 MHz
44.1 11.025 MHz 11.2896 MHz
48 12 MHz 12.288 MHz
NOTE
When DAC_MODE = '01' with the I
2
S or PCM interface operating as master, the stereo
DAC operates at half the frequency of the clock at point B. This divided by two DAC clock
is used as the source clock for the audio port.
The over sampling ratio of the ADC is set by ADC MODE (bit 0 of 0x07h)). The table below shows the required
clock frequency at point C for the different ADC modes.
Table 5. Common ADC Clock Frequencies
ADC Sample Rate (kHz) Clock Required at C (OSR = 125) Clock Required at C (OSR = 128)
8 1 MHz 1.024 MHz
11.025 1.378125 MHz 1.4112 MHz
12 1.5 MHz 1.536 MHz
16 2 MHz 2.048 MHz
22.05 2.75625 MHz 2.8224 MHz
24 3 MHz 3.072 MHz
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