Datasheet
LM49370
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
www.ti.com
BASIC CONFIGURATION REGISTER
This register is used to control the basic function of the chip.
Table 2. BASIC (0x00h)
Bits Field Description
1:0 CHIP_MODE The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode is
selected the LM49370 will change operation silently and will re-configure the power management profile
automatically. The modes are described as follows:
CHIP MODE Audio System Typical Application
00
2
Off Power-down Mode
01
2
Off Stand-by mode with headset event detection
10
2
On Active without headset event detection
11
2
On Active with headset event detection
2 PLL_ENABLE This enables the PLL.
3 USE_OSC If set the power management and control circuits will assume that no external clock is available and will
resort to using an on-chip oscillator for headset detection and analog power management functions such
as click and pop. The PLL, ADC, and DAC are not wired to use this low quality clock. This bit must be
cleared for the part to be fully turned off power-down mode.
5:4 CAP_SIZE This programs the extra delays required to stabilize once charge/discharge is complete, based on the size
of the bypass capacitor.
Bypass Capacitor
CAP_SIZE Turn-off/on time
Size
00
2
0.1 µF 45 ms/75 ms
01
2
1 µF 45 ms/140 ms
10
2
2.2 µF 45 ms/260 ms
11
2
4.7 µF 45 ms/500 ms
7:6 DAC_MODE The DAC can operate in one of four modes. If an “fs*2
∧N
” audio clock is available, then the DAC can be
run in a slightly lower power mode. If such a clock is not available, the PLL can be used to generate a
suitable clock.
DAC MODE DAC OSR Typical Application
48kHz Playback from
00
2
125
12.000MHz
48kHz Playback from
01
2
128
12.288MHz
10
2
64 96kHz Playback from 12.288MHz
11
2
32 192kHz Playback from 24.576MHz
For reliable headset / push button detection the following bits should be defined before enabling the headset
detection system by setting bit 0 of CHIP_MODE:
The OCL-bit (Cap / Capless headphone interface; bit 6 of HP_OUTPUT (0x15h))
The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))
The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))
The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))
All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should
not be altered while the audio sub-system is active.
If the analog or digital levels are below −12dB then it is not necessary to set the stereo bit allowing greater output
levels to be obtained for such signals.
CLOCKS CONFIGURATION REGISTER
This register is used to control the clocks throughout the chip.
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