Datasheet
LM49370
www.ti.com
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012
Status & Control Registers
Table 1. Register Map
(1)
Address Register 7 6 5 4 3 2 1 0
0x00h Table 2 BASIC DAC_ MODE CAP_SIZE OSC_ENB PLL_ENB CHP_MODE
Table 3
0x01h R_DIV DAC_CLK_SEL
CLOCKS
0x02h FORCERQ PLL_M
0x03h PLL_N PLL_N
0x04h PLL_P VCOFATS Q_DIV PLL_P
0x05h PLL_MOD PLLTEST PLL_CLK_SEL PLL_N_MOD
0x06h ADC_1 HPF_MODE SAMPLE_RATE RIGHT LEFT CPI MIC
ADC ADC
0x07h ADC_2 NGZXDD ADC_CLK_SEL PEAKTIME
MUTE _MODE
0x08h AGC_1 NOISE_GATE_THRESHOLD NG_ENB AGC_TARGET AGC_ENB
AGC
0x09h AGC_2 AGC_DECAY AGC_MAX_GAIN
_TIGHT
0x0Ah AGC_3 AGC_ATTACK AGC_HOLD_TIME
0x0Bh MIC_1 INT_EXT SE_DIFF MUTE PREAMP_GAIN
BTN_DEBOUNCE_TIM
0x0Ch MIC_2 BTNTYPE MIC_BIAS_VOLTAGE VCMVOLT
E
0x0Dh SIDETONE SIDETONE_ATTEN
0x0Eh CP_INPUT MUTE CPI_LEVEL
0x0Fh AUX_LEFT AUX_DAC MUTE BOOST AUX_LEFT_LEVEL
0x10h AUX_RIGHT AUX_DAC MUTE BOOST AUX_RIGHT_LEVEL
0x11h DAC USAXLVL DACMUTE BOOST DAC_LEVEL
0x12h CP_OUTPUT MICGATE MUTE LEFT RIGHT MIC
0x13h AUX OUTPUT MUTE LEFT RIGHT CPI
0x14h LS_OUTPUT MUTE LEFT RIGHT CPI
0x15h HP_OUTPUT OCL STEREO MUTE LEFT RIGHT CPI SIDE
0x16h EP_OUTPUT MUTE LEFT RIGHT CPI SIDE
0x17h DETECT HS_DBNC_TIME TEMP_INT BTN_INT DET_INT
0x18h STATUS GPIN1 GPIN2 TEMP BTN MIC STEREO HEADSET
CUST
0x19h 3D ATTENUATE FREQ LEVEL MODE 3DENB
_COMP
WORD_ STEREO I2S_MOD
0x1Ah I2SMODE I2S_WS_GEN_MODE WS_MS INENB OUTENB
ORDER REVERSE E
0x1Bh I2SCLOCK PCM_SYNC__WIDTH I2S_CLOCK_GEN_MODE CLKSCE CLK_MS
ALAW/μLA SDO_
0x1Ch PCMMODE COMPAND SYNC_MS CLKSRCE CLK_MS INENB OUTENB
W LSB_HZ
0x1Dh PCMCLOCK PCM_SYNC_GEN_MODE PCM_CLOCKGEN MODE
MONO_ PCM_
0x1Eh BRIDGE MONO_SUM_MODE DAC_TX_SEL I2S_TX_SEL
SUM_SEL TX_SEL
DAC_SRC_ ADC_SRC_
0x1Fh GPIO GPIO_2_SEL GPIO_1_SEL
MODE MODE
0x20h CMP_0_LSB CMP_0_LSB
0x21h CMP_0_0SB CMP_0_MSB
0x22h CMP_1_LSB CMP_1_LSB
0x23h CMP_1_MSB CMP_1_MSB
0x24h CMP_2_LSB CMP_2_LSB
0x25h CMP_2_MSB CMP_2_MSB
(1) The default value of all I2C registers is 0x00h.
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