Datasheet

CLK
SDI
T
SPISETENB
T
SPIHOLDD
T
SPISETD
T
SPICH
T
SPIT
T
SPICL
T
SPIHOLDENB
TEST_MODE/CS
SDI 15 14
CLK
Ignored8
Register Address
GPIO2
4111
TEST_MODE/CS
Register Data
SDI 15 14 01
CLK
78
Register Address Write Data
TEST_MODE/CS
LM49370
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012 www.ti.com
5 Data Hold Time (Output 300 900 ns
direction, delay generated
by LM49370)
5 Data Hold Time (Input 0 900 ns
direction, delay generated
by the Master)
6 Data Setup Time 100 ns
7 Rise Time of SDA and 20+0.1C
b
300 ns
SCL
8 Fall Time of SDA and SCL 15+0.1C
b
300 ns
9 Set-up Time for STOP 600 ns
condition
10 Bus Free Time between a 1.3 µs
STOP and a START
Condition
C
b
Capacitive Load for Each 10 200 pF
Bus Line
Method 2. SPI/Microwire Control/3–wire Control
The LM49370 can be controlled via a three wire interface consisting of a clock, data and an active low
chip_select. To use this control method connect SPI_MODE to BB_V
DD
and use TEST_MODE/CS as the
chip_select as follows:
Figure 9. SPI Write Transaction
If the application requires read access to the register set; for example to determine the cause of an interrupt
request, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the
GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address
the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to read-
only locations above 0x80h:
Figure 10. SPI Read Transaction
Figure 11. Three Wire Mode Write Bus Timing
Figure 12. SPI Timing
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