Datasheet

ADR6
Bit7
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
MSB LSB
I
2
C SLAVE address (chip address)
SDA
SCL
S
P
START condition
STOP condition
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
LM49370
SNAS356D –FEBRUARY 2007–REVISED MARCH 2012 www.ti.com
System Control
Method 1. I
2
C Compatible Interface
I
2
C SIGNALS
In I
2
C mode the LM49370 pin SCL is used for the I
2
C clock SCL and the pin SDA is used for the I
2
C data signal
SDA. Both these signals need a pull-up resistor according to I
2
C specification. The I
2
C slave address for
LM49370 is 0011010
2
.
I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when SCL is LOW.
Figure 4. I
2
C Signals: Data Validity
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I
2
C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I
2
C master always generates START and STOP bits.
The I
2
C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I
2
C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9
th
clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip address. This address is seven bits long followed by an
eight bit which is a data direction bit (R/W). The LM49370 address is 0011010
2
. For the eighth bit, a “0” indicates
a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
Figure 5. I
2
C Chip Address
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