LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 LM49370 Boomer® Audio Power Amplifier Series Audio Sub-System with an Ultra Low EMI, Spread Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode Stereo Headphone Amplifier, and a Dedicated PCM Interface for Bluetooth Transceivers Check for Samples: LM49370 FEATURES 1 • 2 • • • • • • • • • • • • • • • • • • • • • • • • • Spread Spectrum Class D Architecture Reduces EMI Mono Class D 8Ω Amplifier, 490 mW at 3.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com DESCRIPTION The LM49370 is an integrated audio subsystem that supports both analog and digital audio functions. The LM49370 includes a high quality stereo DAC, a mono ADC, a stereo headphone amplifier, which supports output cap-less (OCL) or AC-coupled (SE) modes of operation, a mono earpiece amplifier, and an ultra-low EMI spread spectrum Class D loudspeaker amplifier.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Application Synthesized FM Radio/ Analog Inputs LM4675 Can Be Used for Stereo Loudspeakers AUX_L AUX_R BYPASS VREF_FLT PLL_FILT AUX_OUT LM4675 GPIO1 0.5-30 MHz LS MCLK BB_VDD EP 2 I C INT_BIAS INT_MIC IRQ Baseband Controller GPIO2 HP_VMIDFB MIC_DET EXT_BIAS EXT_MIC HP_VMID HP_R HP_L 2 I S (Stereo) A2DP Bluetooth Transceiver PCM (Mono) CP_OUT CP_IN LM49370 Radio Module Figure 2.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.
LM49370 www.ti.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Absolute Maximum Ratings www.ti.com (1) (2) Analog Supply Voltage (A_VDD & LS_VDD) 6.0V Digital Supply Voltage (BB_VDD & D_VDD & PLL_VDD) 6.0V −65°C to +150°C Storage Temperature Power Dissipation (3) Internally Limited ESD Susceptibility Human Body Model Machine Model (4) 2500V (5) 200V Junction Temperature 150°C Thermal Resistance θJA – YPG49 (soldered down to PCB with 2in2 1oz.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370 Symbol Parameter Conditions Typical (3) Limit (4) Units (5) Chip Mode '10', fMCLK = 12MHz, fS = 48kHz, DAC on; PLL off 7.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370 Symbol Parameter Conditions Typical (3) Limit (4) Units 25 mW (min) (5) HEADPHONE AMPLIFIER PHP Headphone Power 32Ω load, 3.3V, SE 33 16Ω load, 3.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Electrical Characteristics (1)(2) (continued) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com System Control Method 1. I2C Compatible Interface I2C SIGNALS In I2C mode the LM49370 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for LM49370 is 00110102. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL).
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Register changes take an effect at the SCL rising edge during the last ACK from slave.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com 5 Data Hold Time (Output direction, delay generated by LM49370) 300 900 ns 5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Status & Control Registers Table 1.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com BASIC CONFIGURATION REGISTER This register is used to control the basic function of the chip. Table 2. BASIC (0x00h) Bits Field Description 1:0 CHIP_MODE The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode is selected the LM49370 will change operation silently and will re-configure the power management profile automatically.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Table 3. CLOCKS (0x01h) Bits Field 1:0 DAC_CLK Description This selects the clock to be used by the audio DAC system. DAC_CLK 7:2 R_DIV DAC Input Source 002 MCLK 012 PLL_OUTPUT 102 I2S_CLK_IN 112 PCM_CLK_IN This programs the R divider. R_DIV Divide Value 0 Bypass 1 Bypass 2 1.5 3 2 4 2.5 5 3 6 3.5 7 4 8 4.5 9 5 10 5.5 11 6 12 6.5 13 to 61 7 to 31 62 31.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com USE_ONCHIP_OSC From on chip 12 MHz oscillator %R PLL A (to DET, PMC) B %Q MCLK C I2S Interface Stereo DAC PCM Interface Mono ADC I2S_CLK PCM_CLK Figure 13. LM49370 Clock Network COMMON CLOCK SETTINGS FOR THE DAC & ADC When DAC_MODE = '00' (bits 7:6 of (0x00h)), the DAC has an over sampling ratio of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution as it will work from 12.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Methods for producing these clock frequencies are described in the PLL Section. PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input section of the PLL. Table 6. PLL_M (0x02h) (1) Bits Field 0 RSVD 6:0 PLL_M 7 (1) FORCERQ Description RESERVED PLL_M Input Divider Value 0 No Divided Clock 1 1 2 1.5 3 2 4 2.5 ... 3 to 63 126 63.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Table 8. PLL_P (0x04h) (1) Bits Field 3:0 PLL_P 6:4 7 (1) Q_DIV FAST_VCO Description This programs the PLL output divider as follows: PLL_P Output Divider Value 0 No Divided Clock 1 1 2 1.5 3 2 4 2.5 ... 3 to 7 14 7.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 The complete N divider is a fractional divider as such: N = PLL_N + PLL_N_MOD/32 If the modulus input is zero then the N divider is simply an integer N divider.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Table 11. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 01 Fin (MHz) Fs (kHz) M N P PLL_M PLL_N PLL_N_MO D PLL_P Fout (MHz) 12 48 12.5 64 5 24 64 0 9 12.288 13 48 26.5 112.71875 4.5 52 112 23 8 12.288 14.4 48 37.5 128 4 74 128 0 7 12.288 16.2 48 37.5 128 4.5 74 128 0 8 12.288 16.8 48 12.53 32 3.5 24 32 0 6 12.288 19.2 48 12.5 32 4 24 32 0 7 12.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 ADC_1 CONFIGURATION REGISTER This register is used to control the LM49370's audio ADC. Table 12. ADC_1 (0x06h) Bits Field 0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal. 1 CPI_SELECT If set the cell phone input is added to the ADC input signal. 2 LEFT_SELECT 3 RIGHT_SELECT 5:4 ADC_SAMPLE _RATE Description If set the left stereo bus is added to the ADC input signal.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Table 13. ADC_2 (0x07h) (continued) Bit s Field 4:2 AGC_FRAME_TIME 6:5 7 (1) ADC_CLK NGZXDD Description This sets the frame time to be used by the AGC algorithm.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Table 14. AGC_1 (0x08h) (continued) Bit s Field 7:5 NOISE_ GATE_ THRES Description This field sets the expected background noise level relative to the peak signal level. The sole presence of signals below this level will not result in an AGC gain change of the input and will be gated from the ADC output if the NOISE_GATE_ON is set. This level must be set even if the noise gate is not in use as it is required by the AGC algorithm.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Table 15. AGC_2 (0x09h) (continued) Bits Field 7 AGC_TIGHT AGC_TIGHT = 0 Description If set, the AGC algorithm controls the microphone preamplifier more exactly.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Table 16. AGC_3 (0x0Ah) (continued) Bits Field 7:5 AGC_ATTACK Description This programs the speed at which the AGC will reduce gains if it detects the input level is too large.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a large dynamic range or unknown nominal level.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Table 18. MIC_2 (0x0Ch) (continued) Bits Field Description 2:1 MIC_ BIAS_ VOLTAGE This selects the voltage as a reference to the internal and external microphones. Only one bias pin is driven at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. MIC_BIAS_VOLTAGE should be set to '11' only if A_VDD > 3.4V. In OCL mode, MIC_BIAS_VOLTAGE = '00' (EXT_BIAS = 2.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com SIDETONE ATTENUATION REGISTER This register is used to control the analog sidetone attenuation. (1) Table 20. SIDETONE (0x0Dh) Bits Field 3:0 SIDETONE_ ATTEN (1) Description This programs the attenuation applied to the microphone preamp output to produce a sidetone signal.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 AUX_LEFT CONFIGURATION REGISTER This register is used to control the left aux analog input. Table 22. AUX_LEFT (0x0Fh) Bits Field 4:0 AUX_ LEFT_ LEVEL 5 AUX_ LEFT_ BOOST 6 AUX_L_MUTE 7 AUX_OR_DAC_L (1) Description This programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (1) AUX_LEFT_LEVEL Level (With Boost) Level (Without Boost) 000002 −34.5 dB −46.5 dB 000012 −33 dB −45 dB 000102 −31.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com DAC CONFIGURATION REGISTER This register is used to control the DAC levels to the mixer. Table 24. DAC (0x11h) Bits Field 4:0 DAC_LEVEL Description This programs the gain/attenuation applied to the DAC input to the mixer. (1) DAC_LEVEL Level (With Boost) Level (Without Boost) 000002 −34.5 dB −46.5 dB 000012 −33 dB −45 dB 000102 −31.5 dB −43.5 dB 000112 −30 dB −42 dB 00100 to 111002 −28.5 dB to +7.5 dB −40.5 dB to −4.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 LS_OUTPUT CONFIGURATION REGISTER This register is used to control the loudspeaker output. (1) Table 27. LS_OUTPUT (0x14h) Bits Field 0 CPI_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 LS_MUTE 4 RSVD (1) Description If set, the cell phone input channel of the mixer is added to the loudspeaker output signal. If set, the right channel of the mixer is added to the loudspeaker output signal.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com DETECT CONFIGURATION REGISTER This register is used to control the headset detection system. Table 30. DETECT (0x17h) Bits Field 0 DET_INT If set, an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ that has been triggered by the headset detect. Description 1 BTN_INT If set, an IRQ is raised when the headset button is pressed.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 The LM49370 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel button-type (in parallel with the headset microphone, default value) and series buttontype (in series with the headset microphone) can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch).
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com The wiring of the headset jack to the LM49370 will depend on the intended mode of the headphone amplifier: EXT_MIC_BIAS 3.3/2.8/2.5V MIC_DET 2.2 k: EXT_MIC s s 1 PF LM49370 g Stereo HP_L Cellular g m Stereo + Cellular g m s HP_R s s HP_VMID_FB m = mic s = speaker g = virtual ground HP_VMID 1.2/1.5V Connection for OCL Mode (DC-Coupled) Headset Detection EXT_MIC_BIAS 2.0/2.5V MIC_DET 2.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Table 31. STATUS (0x18h)(1)(2) (continued) Bits Field 3 BTN This field is high when the button on the headset is pressed (only valid if the detection system is enabled). IRQ is cleared when the button has been released and this register has been written to. (2) Description 4 TEMP If this field is high then a temperature event has occurred (write to this register to clear IRQ).
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com I2S PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. Table 33. I2S Mode (0x1Ah) Bit s Field 0 I2S_OUT_ENB 1 I2S_IN_ENB 2 I2S_MODE Description If set, the I2S output bus is enabled. If cleared, the I2S output will be tristate and all RX clocks will be gated. If set, the I2S input is enabled. If this bit cleared, the I2S input is ignored and all TX clocks gated.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Table 34. I2S Clock (0x1Bh) (continued) Bit s Field 5:2 I2S_CLOCK_GEN_MODE 7:6 Description This programs a clock divider that divides the clock defined by I2S_CLOCK_SOURCE. This divided clock is used to generate I2S_CLK in Master mode. (1) PCM_SYNC_WIDTH Value Divide By 00002 1 00012 2 00102 4 00112 6 01002 8 01012 10 01102 16 Ratio 01112 20 — 10002 2.5 2/5 10012 3 1/3 10102 3.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com I2S_CLK I2S_WS I2S_SDO/ I2S_SDI 0 24 23 22 21 3 2 1 0 24 23 22 21 Left Word 3 2 1 0 24 12 11 10 9 Right Word 2 Figure 20. I S Serial Data Format (Left Justified) PCM_CLK PCM_SYNC PCM_SDO/ PCM_SDI 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 Short frame sync mode (PCM_SYNC_WIDTH = '00') Long frame sync mode (PCM_SYNC_WIDTH = '11') Figure 21.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 ADC_CLOCK DAC_CLOCK PCM CLKGEN PCM_CLK_OUT PCM_CLK_IN PCM_CLOCK PCM SYNCGEN PCM_SYNC_OUT PCM_SYNC PCM_SYNC_IN Figure 22. PCM Audio Port CLOCK/SYNC Options PCM PORT CLOCK CONFIGURATION REGISTER This register is used to control the configuration of audio data interfaces. Table 36.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com SRC CONFIGURATION REGISTER (2) This register is used to control the configuration of the Digital Routing interfaces. Table 37. Bridges (0x1Eh) Bits Field 0 PCM_TX_SEL Description This controls the data sent to the PCM transmitter. PCM_TX_SEL 2:1 I2S_TX_SEL Source 0 ADC 1 MONO SUM Circuit This controls the data sent to the I2S transmitter.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 ADC_SRC_MODE PCM_TX_SEL IIR Dec PCM_SDI CIC PCM PCM_SDO Mono ADC Sample & Hold STEREO/ MONO 2 I S_TX_SEL MONO_SUM_MODE MONO_SUM_SEL 2 @FSI DAC_TX_SEL Automatic Handshaking DSDM 2 2 I S_SDI I S I S_SDO FIR Interp Stereo DAC DAC_SRC_MODE Figure 23.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS To allow for compensation of roll off in the DAC and analog filter sections an FIR compensation filter is applied to the DAC input data at the original sample rate. Since the DAC can operate at different over sampling ratios the FIR compensation filter is programmable. By default the filter applies approx 2dB of compensation at 20kHz.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Table 44.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. +3 Stereo DAC Frequency Response fS = 8kHz Stereo DAC Frequency Response Zoom fS = 8kHz +0.5 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.3 -2 -0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. +3 Stereo DAC Frequency Response fS = 32kHz Stereo DAC Frequency Response Zoom fS = 32kHz +0.5 +0.4 +0.3 MAGNITUDE (dB) MAGNITUDE (dB) +2 +1 +0 -1 +0.2 +0.1 +0 -0.1 -0.2 -0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC Frequency Response Zoom fS = 8kHz, 6dB MIC +0.5 +0 +0.4 -10 +0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC Frequency Response Zoom fS = 16kHz, 36dB MIC +0.5 +0 +0.4 -10 +0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC Frequency Response Zoom fS = 32kHz, 6dB MIC +0.5 +0 +0.4 -10 +0.3 -20 +0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. MONO ADC PSRR vs Frequency AVDD = 3.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.2V (AUX inputs terminated) 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) Headphone PSRR vs Frequency AVDD = 3.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 3.3V 0 AUXOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ 10 5 -10 2 1 -20 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Earpiece THD+N vs Frequency AVDD = 5V, 0dB, POUT = 50mW, 32Ω Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.5V, 0dB POUT = 7.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. 10 Headphone THD+N vs Frequency AVDD = 5V, SE, 0dB POUT = 10mW, 32Ω Loudspeaker THD+N vs Frequency AVDD = 3.3V, POUT = 400mW 15μH+8Ω+15μH 10 5 2 2 1 1 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 32Ω Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 16Ω 10 5 10 5 2 1 2 1 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω 10 5 2 1 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω 10 5 2 1 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω 10 5 2 1 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 16Ω 10 5 10 5 2 1 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω 10 5 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω 10 5 2 1 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω 10 5 2 1 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω 10 5 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω 10 5 2 1 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω 10 5 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω 10 5 2 1 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 32Ω 10 5 10 5 2 1 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 32Ω Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 15μH+8Ω+15μH 10 5 2 1 2 1 0.5 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 15μH+8Ω+15μH Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 15μH+8Ω+15μH 10 5 2 1 2 1 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB CPI fOUT = 1kHz, 5kΩ 5 10 5 2 1 0.5 2 1 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ 10 5 2 1 2 1 0.5 0.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Typical Performance Characteristics (continued) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. CPOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ 10 5 10 5 2 1 2 1 0.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Typical Performance Characteristics (continued) CROSSTALK (dB) (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 APPLICATION NOTE MICROPHONE BIAS CONFIGURATIONS Schematic Considerations for MEMs Microphones The internal microphone bias of the LM49370 is provided through a two stage amplifier. Adding a capacitor larger than 100pF directly to this pin can cause instability. In many cases, when using MEMs microphones, a larger bypass capacitor is required on the INT_MIC_BIAS pin.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Class D Loudspeaker To minimize trace resistance and therefore maintain the highest possible output power, the power (LS_VDD) and class D output (LS-, LS+) traces should be as wide as possible. It is also essential to keep these same traces as short and well shielded as possible to decrease the amount of EMI radiation. Capacitors All supply bypass capacitors (for A_VDD, D_VDD.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Demoboard PCB Layout Figure 220. Top Silkscreen Figure 221.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com Figure 222. Mid Layer 1 Figure 223.
LM49370 www.ti.com SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 Figure 224. Bottom Layer Figure 225.
LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com REVISION HISTORY 84 Rev Date 1.0 02/14/07 Initial release. Description 1.01 01/08/08 Fixed a typo on X3 value (Physical Dimension section) in the last page. 1.02 02/11/08 Text edits. 1.03 03/31/11 Input edits and added the section ”PLL LOOP FILTER”. 1.04 05/26/11 Added the Application Note section. 1.05 06/02/11 Edited (tweak) Figures 16 and 17 (schematics for MEM and ECM microphones) respectively.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM49370RL/NOPB DSBGA YPG 49 250 178.0 12.4 LM49370RLX/NOPB DSBGA YPG 49 1000 178.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 4.19 4.19 0.76 8.0 12.0 Q1 4.19 4.19 0.76 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM49370RL/NOPB DSBGA YPG LM49370RLX/NOPB DSBGA YPG 49 250 210.0 185.0 35.0 49 1000 210.0 185.0 35.
MECHANICAL DATA YPG0049xxx D 0.650±0.075 E RLA49XXX (Rev B) D: Max = 3.94 mm, Min = 3.88 mm E: Max = 3.94 mm, Min = 3.88 mm 4214898/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.
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