Datasheet

LM4936
SNAS269A –APRIL 2005–REVISED APRIL 2013 www.ti.com
APPLICATION INFORMATION
I
2
C COMPATIBLE INTERFACE
The LM4936 uses a serial bus, which conforms to the I
2
C protocol, to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I
2
C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4936.
The I
2
C address for the LM4936 is determined using the ID/CE pin. The LM4936's two possible I
2
C chip
addresses are of the form 110110X
1
0 (binary), where X
1
= 0, if ID/CE is logic low; and X
1
= 1, if ID/CE is logic
high. If the I
2
C interface is used to address a number of chips in a system, the LM4936's chip address can be
changed to avoid any possible address conflicts.
The bus format for the I
2
C interface is shown in Figure 53. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I
2
C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4936 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM4936.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM4936 received the
data.
If the master has more data bytes to send to the LM4936, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
I
2
C/SPI INTERFACE POWER SUPPLY PIN (I
2
C/SPI V
DD
)
The LM4936's I
2
C/SPI interface is powered up through the I
2
C/SPI V
DD
pin. The LM4936's I
2
C/SPI interface
operates at a voltage level set by the I
2
C/SPI V
DD
pin which can be set independent to that of the main power
supply pin V
DD
. This is ideal whenever logic levels for the I
2
C/SPI interface are dictated by a microcontroller or
microprocessor that is operating at a lower supply voltage than the main battery of a portable system.
HTSSOP PACKAGE PCB MOUNTING CONSIDERATIONS
HTSSOP (die attach paddle) packages provide a low thermal resistance between the die and the PCB to which
the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper
traces, ground plane and, finally, surrounding air. The result is a low voltage audio power amplifier that produces
2.1W at ≤ 1% THD with a 4Ω load. This high power is achieved through careful consideration of necessary
thermal design. Failing to optimize thermal design may compromise the LM4936's high power performance and
activate unwanted, though necessary, thermal shutdown protection.
The packages must have their exposed DAPs soldered to a grounded copper pad on the PCB. The DAP's PCB
copper pad is connected to a large grounded plane of continuous unbroken copper. This plane forms a thermal
mass heat sink and radiation area. Place the heat sink area on either outside plane in the case of a two-sided
PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer
or backside copper heat sink area with vias. The via diameter should be 0.012in–0.013in with a 1.27mm pitch.
Ensure efficient thermal conductivity by plating-through and solder-filling the vias.
18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4936