Datasheet

LM49350, LM49350RLEVAL
SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012 www.ti.com
Table 72. DAC_ALC_6 (0xA5h)
Bits Field Description
4:0 HOLD_TIME This sets how long the ALC circuit waits before increasing the gain.
HOLDTIME Time (ms)
00000 1
00001 1.25
00010 1.6
00011 2
00100 2.5
00101 3.2
00110 4
00111 5
01000 6.25
01001 8
01010 10
01011 12.5
01100 16
01101 20
01110 25
01111 32
10000 40
10001 50
10010 64
10011 80
10100 100
10101 125
10110 160
10111 200
11000 250
11001 320
11010 400
11011 500
11100 640
11101 800
11110 1000
11111 1250
Table 73. DAC_ALC_7 (0xA6h)
Bits Field Description
5:0 MAX_LEVEL This sets the maximum allowed gain to the digital level control when the ALC is used.
Table 74. DAC_ALC_8 (0xA7h)
Bits Field Description
5:0 MIN_LEVEL This sets the minimum allowed gain to the digital level control when the ALC is used.
82 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: LM49350 LM49350RLEVAL