Datasheet

LM49350, LM49350RLEVAL
www.ti.com SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012
Table 40. CLK_GEN_1 (0x51h/0x61h)
Bits Field Description
5:0 HALF_CYCLE_CLK_DI This programs the half-cycle divider that generates the master clocks in the audio port. The input of
V this divider should be around 12MHz. The default of this divider is 0x00, i.e. bypassed.
Program this divider with the division you want, multiplied by 2, and subtract 1.
HALF_CYCLE_CLK_DIV Divides By
000000 BYPASS
000001 1
000010 1.5
000011 2
— —
111101 31
111110 31.5
11111 32
6 CLOCK_SEL This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.
0 = DAC_SOURCE_CLK
1 = ADC_SOURCE_CLK
Table 41. CLK_GEN_1 (0x52h/62h)
Bits Field Description
2:0 SYNTH_NUM Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in master
mode.
SYNTH_NUM Numerator
000 SYNTH_DENOM (1/1)
001 100/SYNTH_DENOM
010 96/SYNTH_DENOM
011 80/SYNTH_DENOM
100 72/SYNTH_DENOM
101 64/SYNTH_DENOM
110 48/SYNTH_DENOM
111 0/SYNTH_DENOM
3 SYNTH_DENOM Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master
mode.
SYNTH_DENOM Denominator
0 128
1 125
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