Datasheet

0 23 22 21 3 2 1 0 23 22 21 3 2 1 0
I2S_CLK
I2S_SDO/
I2S_SDI
I2S_SYNC
Left Word Right Word
23 22 21 20 2 1 0 23 22 21 20 2 1 0 23
I2S_CLK
I2S_SDO/
I2S_SDI
I2S_SYNC
Left Word Right Word
23 22 21 2 1 0 23 22 21 2 1 0
I2S_CLK
I2S_SDO/
I2S_SDI
I2S_SYNC
Left Word Right Word
LM49350, LM49350RLEVAL
www.ti.com SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012
Table 38. Decimator Input Select (0x45h) (continued)
Bits Field Description
5:4 MXR_CLK_SEL This selects sets the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source
with the highest clock frequency. Whenever the DAC interpolator (DAC_OSR_L or DAC_OSR_R) is selected
then MXR_CLK_SEL should be set to '10'.
MXR_CLK_SEL Selected Input
00 Auto
01 MCLK
10 DAC
11 ADC
Audio Port Control Registers
Figure 59. I
2
S Serial Data Format (24 bit example)
Figure 60. Left Justified Data Format (24 bit example)
Figure 61. Right Justified Data Format (24 bit example)
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