Datasheet

LM49350, LM49350RLEVAL

SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012

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Table 30. ADC TRIM (0x22h)

Bits Field Description

7:0 ADC_TRIM If set, the ADC is compensated with recommended compensation filter coefficients. The recommended

ADC compensation filter coefficients are programmed as follows:

DAC Control Registers

This register is used to control the LM49350's DAC:

Table 31. DAC Basic (0x30h)

Bits Field Description

1:0 MODE This programs the over sampling ratio of the stereo DAC.

MODE DAC Oversampling Ratio

00 125

01 128

10 64

11 32

2 MUTE_L This digitally mutes the Left DAC output.

3 MUTE_R This digitally mutes the Right DAC output.

6:4 DAC_CLK_SEL This selects the source of the DAC clock domain, DAC_SOURCE_CLK.

DAC_CLK_SEL Source

000 MCLK

001 PORT1_RX_CLK

010 PORT2_RX_CLK

011 PLL1_OUTPUT1

100 PLL2_OUTPUT

7 DSP_ONLY If set, the DAC's analog circuitry is disabled to reduce power consumption, however DAC DSP

functionality is maintained. This can be used to perform asyncronous resampling between audio rates of

a common family.

Table 32. DAC_CLK_DIV (0x31h)

Bits Field Description

7:0 DAC_CLK_DIV This programs the half cycle divider that precedes the DAC. The input of this divider should be around

12MHz. The default of this divider is 0x00.

Program this divider with the division you want, multiplied by 2, and subtract 1.

DAC_CLK_DIV Divides by

00000000 1

00000001 1

00000010 1.5

00000011 2

— —

11111101 127

11111110 127.5

11111111 128

Product Folder Links: LM49350 LM49350RLEVAL