Datasheet

LM49350, LM49350RLEVAL
SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012 www.ti.com
Table 7. PLL Settings for Common System Clock Frequencies (continued)
f
IN
(MHz) M N N_MOD P f
OUT
(MHz) Error (Hz)
16.8 7 85 0 17 12000000 0
19.2 8 85 0 17 12000000 0
19.68 20.5 200 0 16 12000000 0
19.8 16.5 170 0 17 12000000 0
11.2896 8 125 0 16 11025000 0
12 10 147 0 16 11025000 0
12.288 8 114 27 16 11025000 0
13 6.5 96 15 17.5 11025000 0
13.5 10 147 0 18 11025000 0
14.4 4 49 0 16 11025000 0
16.2 4 49 0 18 11025000 0
16.8 16 189 0 18 11025000 0
19.2 16 147 0 16 11025000 0
19.68 16 189 0 18 11025000 0
19.8 16 147 0 16.5 11025000 0
Table 8. PLL_CLOCK_SOURCE (0x03h)
Bits Field Description
1:0 PLL1_CLK_SEL This selects the source of the input clock to PLL1
PLL1_CLK_SEL PLL1 Input Clock Source
00 MCLK
01 PORT1_CLK
10 PORT2_CLK
11 RESERVED
Table 9. PLL1_M (0x04h)
Bits Field Description
6:0 PLL1_M This programs the PLL1 M divider to divide from 1 to 64.
PLL1_M PLL1 Input Divider Vaue
000000 1
000001 1
000010 1.5
000011 2
000100 2.5
000101 3
— —
1111101 63
1111110 63.5
1111111 64
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