Datasheet

LM49350, LM49350RLEVAL
www.ti.com SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012
The LM49350 contains two PLLs for flexible operation of its dual audio ports. PLL1 has a P1 and P2 output
divider thereby allowing PLL1 to generate two distinct clock outputs. The equations for PLL1's generated output
clocks are as follows:
f
OUT1
= (f
IN
. N
1
/ M
1
. P
1
) (1)
f
OUT2
= (f
IN
. N
1
/ M
1
. P
2
) (2)
where:
N
1
= PLL1_N + PLL1_N_MOD (3)
M
1
= (PLL1_M + 1) / 2 (4)
P
1
= (PLL1_P1 + 1) / 2 (5)
P
2
= (PLL1_P2 + 1) / 2 (6)
The equations for PLL2's generated output clock are as follows:
f
OUT3
= (f
IN
.N
2
/ M
2
.P) (7)
where:
N
2
= PLL2_N + PLL2_N_MOD (8)
M
2
= (PLL2_M + 1) / 2 (9)
P = (PLL2_P + 1) / 2 (10)
The VCO frequency and comparison frequencies are as follows:
f
VCO
= f
OUT
.P (11)
f
COMP
= f
IN
/M (12)
Keep f
VCO
between 140MHz to 240MHz and keep f
COMP
between 700kHz to 5MHz.
Table 7. PLL Settings for Common System Clock Frequencies
f
IN
(MHz) M N N_MOD P f
OUT
(MHz) Error (Hz)
12 2.5 32 0 12.5 12288000 0
13 15.5 175 26 12 12287970 –30
14.4 12.5 128 0 12 12288000 0
16.2 13.5 128 0 12.5 12288000 0
16.8 3.5 32 0 12.5 12288000 0
19.2 12.5 96 0 12 12288000 0
19.68 20.5 160 0 12.5 12288000 0
19.8 16.5 128 0 12.5 12288000 0
27 22.5 128 0 12.5 12288000 0
12 12.5 147 0 12.5 11289600 0
12.288 10 147 0 16 11289600 0
13 9 144 19 18.5 11289603 +3
13.5 15.5 213 28 16.5 11289589 –11
14.4 12.5 147 0 15 11289600 0
16.2 22.5 196 0 12.5 11289600 0
16.8 12.5 126 0 15 11289600 0
19.2 20 147 0 12.5 11289600 0
19.68 20.5 147 0 12.5 11289600 0
19.8 27.5 196 0 12.5 11289600 0
27 37.5 196 0 12.5 12289600 0
11.2896 10.5 195 0 17.5 12000000 0
12.288 8 125 0 16 12000000 0
13 6.5 102 0 17 12000000 0
13.5 4.5 68 0 17 12000000 0
14.4 6 85 0 17 12000000 0
16.2 13.5 170 0 17 12000000 0
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