Datasheet

PLL_P
1 ± 25 MHz
P1 = 0,1 + 0/2
_
> 256
8
PLL_M
PLL_N_MOD
7
5
9
% N
% P
VCO
6
'M
140 to 240 MHz
0.7 < 5 MHz
% M
N=0, 1 + 0/32
_
> 250
Phase Comparator
and Charge Pump
P= 0.1 + 0/2
_
> 64
0.5 - 50 MHz
PLL_N
I
8
9
PLL_P2
P2A = 0,1 + 0/2
_
> 256
1 ± 25 MHz
1 ± 25 MHz
P2B = 0,1 + 0/2
_
> 256
PLL_P2
8
PLL_M
PLL_N_MOD
7
5
9
% N
% P1
% P2
VCO
6
'M
140 to
210 MHz
0.7 < 5 MHz
% M
N=0, 1 + 0/32
_
> 250
Phase Comparator
and Charge Pump
P= 0.1 + 0/2
_
> 64
0.5 - 50 MHz
PLL_N
I
8
-300 kHz
MCLK
0
_
> 50 MHz
0
_
50 MHz
OSCILLATOR
INTERNAL
PORT2_CLK
AUDIO PORT 1
PMC
Stereo DAC
MIXER
Stereo ADC
PLL1
% S
1
±
25
MHz
R, S, T = Half Cycle 1, 1.5, 2, 2.5
_
> 128
% T
% R
PLL2
AUDIO PORT 2
PORT1_CLK
0
_
50 MHz
A
B
C
LM49350, LM49350RLEVAL
SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012 www.ti.com
Figure 54. Internal Clock Network
PLL Setup Registers
Figure 55. PLL1 Loop
Figure 56. PLL2 Loop
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