Datasheet

LM49350, LM49350RLEVAL
www.ti.com SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012
The LM49350's Power Management Circuit (PMC) requires a clock that is independent from the DAC or ADC. It
is recommended to provide a ≈300kHz clock at Point C. The PMC clock divider (R divider) is available to
generate the correct clock to the PMC block. The PMC clock path can be driven directly by the MCLK input, the
internal 300kHz oscillator, the DAC_SOURCE_CLK, or the ADC_SOURCE_CLK.
Table 5. DAC Clock Requirements
DAC Sample Rate Clock Required at A Clock Required at A Clock Required at A Clock Required at A
(kHz) (OSR = 128) (OSR= 125) (OSR = 64) (OSR = 32)
8 2.048 MHz 2 MHz 1.024 MHz 0.512 MHz
11.025 2.8224 MHz 2.75625 MHz 1.4112 MHz 0.7056 MHz
12 3.072 MHz 3 MHz 1.536 MHz 0.768 MHz
16 4.096 MHz 4 MHz 2.048 MHz 1.024 MHz
22.05 5.6448 MHz 5.5125 MHz 2.8224 MHz 1.4112 MHz
24 6.144 MHz 6 MHz 3.072 MHz 1.536 MHz
32 8.192 MHz 8 MHz 4.096 MHz 2.048MHz
44.1 11.2896 MHz 11.025 MHz 5.6448 MHz 2.8224 MHz
48 12.288 MHz 12 MHz 6.144 MHz 3.072 MHz
96 24.576 MHz 24 MHz 12.288 MHz 6.144 MHz
192 — — 24.576 MHz 12.288 MHz
Table 6. ADC Clock Requirements
ADC Sample Rate Clock Required at B Clock Required at B Clock Required at B
(kHz) (OSR = 128) (OSR= 125) (OSR = 64)
8 2.048 MHz 2 MHz 1.024 MHz
11.025 2.8224 MHz 2.75625 MHz 1.4112 MHz
12 3.072 MHz 3 MHz 1.536 MHz
16 4.096 MHz 4 MHz 2.048 MHz
22.05 5.6448 MHz 5.5125 MHz 2.8224 MHz
24 6.144 MHz 6 MHz 3.072 MHz
32 8.192 MHz 8 MHz 4.096 MHz
44.1 11.2896 MHz 11.025 MHz 5.6448 MHz
48 12.288 MHz 12 MHz 6.144 MHz
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