Datasheet

LM49350, LM49350RLEVAL
SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012 www.ti.com
PMC Clocks Register
This register is used to control the LM49350's Basic Power Management Setup:
Table 3. PMC_SETUP (0x01h)
Bits Field Description
1:0 PMC_CLK_SEL This selects the source of the PMC input clock.
PMC_CLK_SEL PMC Input Clock Source
00 MCLK (Default divide is 40)
01 Internal 300kHz Oscillator
10 DAC SOURCE CLOCK
11 ADC SOURCE CLOCK
PMC Clock Divide Register
This register is used to control the LM49350's Power Management Circuits Clocks:
Table 4. PMC_SETUP (0x02h) (Default data value is 0x50h)
Bits Field Description
7:0 PMC_CLK_DIV This programs the half cycle divider that precedes the PMC. The PMC should run from a
300kHz clock. The default of this divider is 0x50h (divide by 40) to get a ≈300kHz PMC clock
from a 12MHz or 12.288MHz MCLK.
Program this divider with the division you want, multiplied by 2, and subtract 1.
PMC_CLK_DIV Divide by
00000000 1
00000001 1
00000010 1.5
00000011 2
00000100 2.5
00000101 3
— —
11111101 126
11111110 127.5
11111111 128
LM49350 Clock Network
Refer to Figure 54
The audio DAC and ADC operate at a clock frequency of 2*OSR*f
S
where OSR is the oversampling ratio and f
S
is the sampling frequency of the DAC or ADC. The DAC can operate at four different OSR settings (128, 125, 64,
32). The ADC can operate at three different OSR settings (128, 125, 64). For example, if the stereo DAC or ADC
is set at OSR = 128, a 12.288MHz clock is required for 48kHz data. If a 12.288MHz clock is not available, then
one of the LM49350's dual PLLs can be used to generate the desired clock frequency. Otherwise, if a
12.288MHz is available, then the PLL can be bypassed to reduce power consumption. The DAC clock divider (S
divider) or ADC clock divider (T divider) can also be used to generate the correct clock. If an 18.432 MHz clock is
available, the S or T divider could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without
using a PLL.
The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by
the MCLK input, the PORT1_CLK input, the PORT2_CLK input, PLL1's output, or PLL2's output.
For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to
PLL1 or PLL2 can come from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.
32 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: LM49350 LM49350RLEVAL