Datasheet

LM49350, LM49350RLEVAL
www.ti.com
SNAS359D SEPTEMBER 2008REVISED JUNE 2012
Basic PMC Setup Register
This register is used to control the LM49350's Basic Power Management Setup:
Table 2. PMC_SETUP (0x00h)
Bits Field Description
When this bit is set the power management will enable the MCLK I/O or internal oscillator
(1)
. It
will then use this clock to sequence the enabling of the analog references and bias points.
When this bit is cleared the PMC will bring the analog down gently and disable the MCLK or
oscillator.
0 CHIP_ENABLE
CHIP _ENABLE Chip Status
0 Turn Chip Off
1 Turn Chip On
This enables the primary PLL
PLL1_ENABLE PLL1 Status
1 PLL1_ENB
0 PLL1 Off
1 PLL1 On
This enables the secondary PLL
PLL2_ENABLE PLL2 Status
2 PLL2_ENB
0 PLL2 Off
1 PLL2 On
This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can be
used instead of an external system clock to drive the chip's power management (PMC).
OSC_ENABLE Oscillator Status
3 OSC_ENB
0 Oscillator Off
1 Oscillator On
This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and
digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK
is selected as the clock source and that there is an active clock signal driving the MCLK pin.
Setting this bit reduces power consumption, by allowing audio ports and digital mixer to
operate while the analog sections of the chip is powered down.
4 MCLK_OVR
MCLK_OVR Comment
0 I/O control is automatic
1 MCLK input forced on.
This forces the clock input of Audio Port 1 input to enable, regardless of other port settings.
PORT1_CLK_OVR Comment
5 PORT1_CLK_OVR
0 I/O control is automatic
1 PORT_CLK input forced on
This forces the clock input of Audio Port 2 input to enable, regardless of other port settings.
PORT2_CLK_OVR Comment
6 PORT2_CLK_OVR
0 I/O control is automatic
1 PORT_CLK input forced on
7 CHIP_ACTIVE This bit is used to read back the enable status of the chip.
(1) If the PMC is set to operate from one of the audio ports then it will wait for the port to be enabled or the relevant over ride bit to be set,
forcing the port clock input to enable.
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