Datasheet

LM49350, LM49350RLEVAL
www.ti.com SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012
Device Register Map
Table 1. Device Register Map
(1)
Address Register 7 6 5 4 3 2 1 0
BASIC SETUP
PMC CHIP PORT2 PORT1 MCLK OSC PLL2 PLL1 CHIP
0x00h
SETUP ACTIVE CLK OVR CLK OVR OVR ENB ENB ENB ENABLE
PMC
0x01h PMC_CLK_SEL
CLOCKS
PMC
0x02h PMC_CLK_DIV(R)
CLK_DIV
PLLs
0x03h PLL2_CLK_SEL PLL1_CLK_SEL
0x04h PLL1 M PLL1 M
0x05h PLL1 N PLL1 N
PLL1
0x06h PLL2 P2[8] PLL1 P1[8] PLL1 N_MOD
N_MOD
0x07h PLL1 P1 PLL1 P1 [7:0]
0x08h PLL1 P2 PLL1 P2[7:0]
0x09h PLL2 M PLL2 M
0x0Ah PLL2 N PLL2 N
PLL2
0x0Bh PLL2 P[8] PLL2 N_MOD
N_MOD
0x0Ch PLL2 P PLL2 P[7:0]
ANALOG MIXER
0x10h CLASSD AUXL_LS AUXR_LS MICL_LS MICR_LS DACL_LS DACR_LS
HEAD
DACR_HPL
0x11h AUXL_HPL AUXR_HPL MICL_HPL MICR_HPL DACL_HPL
PHONESL
HEAD
AUXR_ DACL_ DACR_
0x12h AUXL_HPR MICL_HPR MICR_HPR
HPR HPR HPR
PHONESR
0x13h AUX_OUT AUXL_AX AUXR_AX MICL_AX MICR_AX DACL_AX DACR_AX
OUTPUT CP_
0x14h AUX-6dB LS-6dB HP-6dB EPMODE
OPTIONS FORCE
AUXL_ AUXR_ MICL_ MICR_ DACL_ DACR_
0x15h ADC
ADCR ADCL ADCR ADCL ADCR ADCL
0x16h MICL_LVL MUTE SE/DIFF MIC_L_LEVEL
0x17h MICR_LVL MUTE SE/DIFF MIC_R_LEVEL
FROM
0x18h AUXL_LVL AUX_L_LEVEL
LINEL
FROM
0x19h AUXR_LVL DIFF_MODE AUX_R_LEVEL
LINER
ADC
0x20h ADC BASIC DSPONLY ADC_CLK_SEL MUTE_R MUTE_L ADC_OSR MONO
ADC
0x21h ADC_CLK_DIV (T)
CLOCK
0x22h ADC_DSP ADC_TRIM
DAC
DAC_BASI
0x30h DSPONLY DAC_CLK_SEL MUTE_R MUTE_L DAC_OSR
C
DAC_CLOC
0x31h DAC_CLK_DIV (S)
K
0x32h DAC_DSP DAC_TRIM
(1) Unless otherwise specified, the default values of the I
2
C registers is 0x00h.
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