Datasheet

I2S_CLK
I2S_WS
I2S_SDI
t
DST
t
DHT
T
WS_ST
I2S_SDO
T
SDO
_
DLY
T
WS_HT
(CLK_PHASE = 0)
I2S_CLK
PER
TCLK_H TCLK_L
I2S_CLK
I2S_WS
I2S_SDO
T
WS_DLY
I2S_CLK
PER
T
SDO
_
DLY
I2S_SDI
t
DST
t
DHT
(CLK_PHASE = 0)
TCLK_H TCLK_L
LM49350, LM49350RLEVAL
SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012 www.ti.com
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
Figure 7. Timing for I
2
S Master
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
Figure 8. Timing for I
2
S Slave
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