Datasheet
SYNC
BIT_CLK
SDATA_IN
SDATA_OUT
T
RISE
T
FALL
10%
90% 90%
10%
BIT_CLK
SDATA_IN
T
CO
T
DHOLD
T
DSETUP
SYNC
T
SSETUP
T
SHOLD
SDATA_OUT
SYNC
T
SH
T
SL
T
SP
T
BCH
T
BCL
T
BCP
BIT_CLK
OBSOLETE
LM4550
SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
www.ti.com
Electrical Characteristics (continued)
The following specifications apply for AV
DD
= 5V, DV
DD
= 5V, Fs = 48 kHz, single codec configuration, unless otherwise
noted. Limits apply for T
A
= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.
(1)(2)
LM4550
Units
Symbol Parameter Conditions
(Limits)
Typical
(3)
Limit
(4)
Data Delay from CIN to SDATA_IN when
T
CS
Chain Propagation Delay TBD TBD ns (max)
the chain feature is active
T
RST_LOW
RESET# active low pulse width For Cold Reset 1.0 µs (min)
T
RST2CLK
RESET# inactive to BIT_CLK start up For Cold Reset TBD 162.8 ns (min)
T
SH
SYNC active high pulse width For Warm Reset 1.3 TBD µs (min)
T
SYNC2CLK
SYNC inactive to BIT_CLK start up For Warm Reset TBD 162.8 ns (min)
Delay from end of Slot 2 to BIT_CLK,
T
S2_PDOWN
AC Link Power Down Delay 1 µs (max)
SDATA_IN low
Time from minimum valid supply levels to
T
SUPPLY2RST
Power On Reset 1 µs (min)
end of Reset
T
SU2RST
Setup to trailing edge of RESET# For ATE Test Mode 15 ns (min)
T
RST2HZ
Rising edge of RESET# to Hi-Z For ATE Test Mode 25 ns (max)
Timing Diagrams
Figure 1. Clocks
Figure 2. Data Delay, Setup and Hold
Figure 3. Digital Rise and Fall
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