Datasheet
OBSOLETE
LM4550
www.ti.com
SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
Electrical Characteristics (continued)
The following specifications apply for AV
DD
= 5V, DV
DD
= 5V, Fs = 48 kHz, single codec configuration, unless otherwise
noted. Limits apply for T
A
= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.
(1)(2)
LM4550
Units
Symbol Parameter Conditions
(Limits)
Typical
(3)
Limit
(4)
THD Total Harmonic Distortion V
IN
= -3 dB, f = 1 kHz, R
L
= 10 kΩ 0.01 %
Frequency Response 20 - 21 k Hz
Group Delay
(6)
2 ms (max)
Out of Band Energy
(7)
-40 dB
Stop Band Rejection 70 dB
D
T
Discrete Tones -96 dB
Analog Output Section
A
S
Step Size 0 dB to -46.5 dB 1.5 dB
A
M
Mute Attenuation 86 dB
Headphone Amplifier Total Harmonic Loopthrough Mode
(5)
, R
L
= 32 Ω, f = 1 kHz,
THD+N 0.02 %
Distortion plus Noise P
out
= 50 mW
Z
OUT
Output Impedance
(6)
HP_OUT_L, HP_OUT_R TBD Ω
Z
OUT
Output Impedance
(6)
LINE_OUT_L, LINE_OUT_R, MONO_OUT TBD Ω
Digital I/O
(6)
0.40 x
V
IH
High level input voltage V (min)
DV
DD
0.30 x
V
IL
Low level input voltage V (max)
DV
DD
0.50 x
V
OH
High level output voltage V (min)
DV
DD
0.20 x
V
OL
Low level output voltage V (max)
DV
DD
I
L
Input Leakage Current AC Link inputs ±10 µA
I
L
Tri state Leakage Current High impedance AC Link outputs ±10 µA
I
DR
Output drive current AC Link outputs 5 mA
Digital Timing Specifications
(8)
F
BC
BIT_CLK frequency 12.288 MHz
T
BCP
BIT_CLK period 81.4 ns
T
CH
BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20 % (max)
F
SYNC
SYNC frequency 48 kHz
T
SP
SYNC period 20.8 µs
T
SH
SYNC high pulse width 1.3 µs
T
SL
SYNC low pulse width 19.5 µs
T
DSETUP
Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 15 ns (min)
Hold time of SDATA_OUT from falling edge
T
DHOLD
Hold Time for codec data input 5 ns (min)
of BIT_CLK
T
SSETUP
Setup Time for codec SYNC input SYNC to rising edge of BIT_CLK TBD ns (min)
Hold time of SYNC from rising edge of
T
SHOLD
Hold Time for codec SYNC input TBD ns (min)
BIT_CLK
Output Delay of SDATA_IN from rising
T
CO
Output Valid Delay TBD 15 ns (max)
edge of BIT_CLK
BIT_CLK, SYNC, SDATA_IN or
T
RISE
Rise Time 6 ns (max)
SDATA_OUT
BIT_CLK, SYNC, SDATA_IN or
T
FALL
Fall Time 6 ns (max)
SDATA_OUT
(7) Out of band energy is measured from 28.8 kHz to 100 kHz relative to a 1 Vrms DAC output.
(8) These specifications are ensured by design and characterization; they are not production tested.
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