Datasheet

OBSOLETE
LM4550
SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013 www.ti.com
Multiple Codecs
EXTENDED AC LINK
Up to four codecs can be supported on the extended AC Link. These multiple codec implementations should run
off a common BIT_CLK generated by the Primary Codec. All codecs share the AC '97 Digital Controller output
signals, SYNC, SDATA_OUT, and RESET#. Each codec, however, supplies its own SDATA_IN signal back to
the controller, with the result that the controller requires one dedicated input pin per codec (Figure 25).
By definition there can be one Primary Codec and up to three Secondary Codecs on an extended AC Link. The
Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00 while Secondary Codecs take identities equal to 01,
10 or 11 (see Table 19). The Codec Identity is also used as a chip select function. This allows the Command and
Status registers in any of the codecs to be individually addressed although the access mechanism for Secondary
Codecs differs slightly from that for a Primary.
The Identity control pins, ID1#, ID0# (pins 46 and 45) are internally pulled up to DV
DD
. The Codec may therefore
be configured as 'Primary' either by leaving ID1#, ID0# open (NC) or by strapping them externally to DV
DD
(digital
supply).
The difference between Primary and Secondary codec modes is: in their timing source; in the AMAP Slot-to-DAC
mapping used in Output Frames carried by SDATA_OUT; and in the Tag Bit handling in Output Frames for
Command/Status register access. For a timing source, a Primary codec divides down by 2 the frequency of the
signal on XTAL_IN and also generates this as the BIT_CLK output for the use of the controller and any
Secondary codecs. Secondary codecs use BIT_CLK as an input and as their timing source and do not use
XTAL_IN or XTAL_OUT, The AMAP mappings are given in Table 19 and the use of Tag Bits is described below.
SECONDARY CODEC REGISTER ACCESS
For Secondary Codec access, the controller must set the tag bits for Command Address and Data in the Output
Frame as invalid (i.e. equal to 0). The Command Address and Data tag bits are in slot 0, bits 14 and 13 and
Output Frames are those in the SDATA_OUT signal from controller to codec. The controller must also place the
non-zero value (01, 10, or 11) corresponding to the Identity (ID1, ID0) of the target Secondary Codec into the
Codec ID field (slot 0, bits 1 and 0) in that same Output Frame. The value set in the Codec ID field determines
which of the three possible Secondary Codecs is accessed. Unlike a Primary Codec, a Secondary Codec will
disregard the Command Address and Data tag bits when there is a match between the 2-bit Codec ID value (slot
0, bits 1 and 0) and the Codec Identity (ID1, ID0). Instead it uses the Codec-ID/Identity match to indicate that the
Command Address in slot 1 and (if a “write”) the Command Data in slot 2 are valid.
When reading from a Secondary Codec, the controller must send the correct Codec ID bits (i.e. the target Codec
Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) and target register address (slot 1,
bits 18 – 12). To write to a Secondary Codec, a controller must send the correct Codec ID bits when slot 1
contains a valid target register address and “write” indicator bit and slot 2 contains valid target register data. A
write operation is only valid if the register address and data are both valid and sent within the same frame. When
accessing the Primary Codec, the Codec ID bits are cleared and the tag bits 14 and 13 resume their role
indicating the validity of Command Address and Data in slots 1 and 2.
The use of the tag bits in Input Frames (carried by the SDATA_IN signal) is the same for Primary and Secondary
Codecs.
The Codec Identity is determined by the inverting input pins ID1#, ID0# (pins 46 and 45) and can be read as the
value of the ID1, ID0 bits (D15, D14) in the Extended Audio ID register, 28h of the target codec.
In addition to the Codec Identity bits (ID1, ID0), the read-only Extended Audio ID register (28h) contains the
AMAP bit (D9). The AMAP bit indicates support for the (optional) AC '97 Rev. 2.1 compliant mappings from slots
in AC Link Output Frames to the audio DACs for each of the four Codec Identity modes. AMAP = 1 indicates that
the default mapping (as realized after reset) of Slots-to-DACs conforms to Table 19. Slots in AC Link Input
Frames are always mapped such that PCM data from the left ADC channel is carried by slot 3 and PCM data
from the right ADC channel by slot 4. Output Frames are those carried by the SDATA_OUT signal from the
controller to the codec while Input Frames are those carried by the SDATA_IN signal from the codec to the
controller.
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