Datasheet

SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
Slot 12
Prev. Frame
TAG
TAG
Slot 0
Slot 12
Prev. Frame
Write to
REG. 26h
Data
PR4 = 1
Note: BIT_CLK and data transitions are not to scale
T
S2_PDOWN
Slot 1 Slot 2
OBSOLETE
LM4550
www.ti.com SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
PR0 controls the powerdown state of the ADC and associated sampling rate conversion circuitry. PR1 controls
powerdown for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits
(MIX1, MIX2, National 3D Sound, Mono Out, Line Out). PR3 powers down V
REF
in addition to all the same mixer
circuits as PR2. PR4 powers down the AC Link Digital Interface – see Figure 24 for signal powerdown timing.
PR5 disables internal clocks but leaves the crystal oscillator and BIT_CLK running (needed for minimum Primary
mode powerdown dissipation in multi-codec systems). PR6 powers down the Headphone amplifier. EAPD
controls the External Amplifier PowerDown pin (pin 47).
After a subsection has undergone a powerdown cycle, the appropriate status bit(s) in the Powerdown
Control/Status register (26h) must be polled to confirm readiness. In particular the startup time of the V
REF
circuitry depends on the value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF in parallel is
recommended).
When the AC Link Digital Interface is powered down the codec output signals SDATA_IN and BIT_CLK (Primary
mode) are cleared to zero and no control data can be passed between controller and codec(s). This powerdown
state can be cleared in two ways: Cold Reset (RESET# = 0) or Warm Reset (SYNC = 1, no BIT_CLK). Cold
Reset sets all registers back to their default values (including clearing PR4) whereas Warm Reset only clears the
PR4 bit and restarts the AC Link Digital Interface leaving all register contents otherwise unaffected. For Warm
Reset (see Timing Diagrams), the SYNC input is used asynchronously. The LM4550 codec allows the AC Link
digital interface powerdown state to be cleared immediately so that its duration can essentially be as short as
T
SH
, the Warm Reset pulse width. However for conformance with AC '97 Rev 2.1, Warm Reset should not be
applied within 4 frame times of powerdown i.e. the AC Link powerdown state should be allowed to last at least
82.8 µs.
Figure 24. AC Link Powerdown Timing
Improving System Performance
The audio codec is capable of dynamic range performance in excess of 90 db., but the user must pay careful
attention to several factors to achieve this. A primary consideration is keeping analog and digital grounds
separate, and connecting them together in only one place. Some designers show the connection as a zero ohm
resistor, which allows naming the nets separately. Although it is possible to use a two layer board, it is
recommended that a minimum of four layers be used, with the two inside layers being analog ground and digital
ground. If EMI is a system consideration, then as many as eight layers have been successfully used. The 12 and
25 MHz. clocks can have significant harmonic content depending on the rise and fall times. With the exception of
the digital VDD pins, (covered later) bypass capacitors should be very close to the package. The analog VDD
pins should be supplied from a separate regulator to reduce noise. By operating the digital portion on 3.3V
instead of 5V, an additional 0.5-0.7 db improvement can be obtained.
Depending on power supply layout, routing, and capacitor ESR, a device instability can occur, resulting in
increased noise on the outputs. This can be eliminated by adding an inductor in the digital supply line between
the supply bypass capacitors and the DVDD pins, which increases the high frequency impedance of the supply
as seen by the part. This “current starving” technique slows down internal rise and fall times, which will improve
the signal to noise ratio, especially at low temperatures. In addition, the EMI radiated from the board is also
reduced.
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