Datasheet

OBSOLETE
LM4550
SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013 www.ti.com
Table 18. Common Sample Rates
SR15:SR0 Sample Rate (Hz)
1F40h 8000
2B11h 11025
3E80h 16000
5622h 22050
AC44h 44100
*BB80h *48000
CHAIN-IN CONTROL REGISTER (74h)
This read/write register is only needed when using the Chain In feature. This feature goes beyond the AC '97
specification and is not required for standard AC Link operation. The two LSBs of this register default to the
Codec Identity (ID1, ID0) after reset. This default state corresponds to standard AC Link operation where the
output of codec pin 8 (SDATA_IN) carries the AC Link Input Frames back to the controller from the codec.
If the two LSBs differ from the Codec Identity (register 28h describes the Codec Identity), then the signal present
at CIN (pin 48) is switched through to the SDATA_IN (pin 8) output. In this fashion, Secondary codecs can be
chained together by connecting one codec's SDATA_IN pin to the next codec's CIN pin. This has the end result
of only requiring a single SDATA_IN pin at the controller rather than the standard one SDATA_IN pin per codec.
Note, however, that the chained codecs time-share the bandwidth of the SDATA_IN signal under allocation from
the controller.
The first codec in the chain (nearest the controller) will have access to the full bandwith of SDATA_IN following a
system reset (Cold Reset for each codec). To access any other codec in the chain, the controller must write a
suitable value (i.e. the Identity of the target codec) to the Chain-In Control register (74h) of each intervening
codec in the chain.
The last codec in the serial chain (furthest from the controller) should have its CIN pin connected to digital
ground. When writing software drivers, care should be taken to avoid any problems that could occur when this
last codec in the chain is set to pass a CIN signal when there is none to pass. Different controllers may handle
an input of all 0s differently and leaving the CIN pin floating should definitely be avoided.
BIT# Function
*(bit1,bit0) = (ID1,ID0): Chain-In off
1,0
(bit1,bit0) ≠ (ID1,ID0): Chain-In on
VENDOR ID REGISTERS (7Ch, 7Eh)
These two read-only (4E53h, 4350h) registers contain National's Vendor ID and National's LM45xx codec version
designation. The first 24 bits (4Eh, 53h, 43h) represent the three ASCII characters “NSC” which is National's
Vendor ID for Microsoft's Plug and Play. The last 8 bits are the two binary coded decimal characters, 5, 0 and
identify the codec to be an LM4550.
RESERVED REGISTERS
Do not write to reserved registers. In particular, do not write to registers 24h, 5Ah and 7Ah. All registers not listed
in the LM4550 Register Map are reserved. Reserved registers will return 0000h if read.
Low Power Modes
The LM4550 provides 7 bits to control the powerdown state of internal analog and digital subsections and clocks.
It also provides one bit intended to control an external analog power amplifier. These 8 bits (PR0 – PR6, EAPD)
are the 8 MSBs of the Powerdown Control/Status register, 26h. The status of the four main analog subsections is
given by the 4 LSBs in the same register, 26h.
The powerdown bits are implemented in compliance with AC '97 Rev 2.1 to support the standard device power
management states D0 – D3 as defined in the ACPI and PCI Bus Power Management specification.
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