Datasheet
OBSOLETE
LM4550
www.ti.com
SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
BIT# BIT Function: Status
0 ADC 1 = ADC section ready to transmit data
1 DAC 1 = DAC section ready to accept data
2 ANL 1 = Analog mixers ready
3 REF 1 = V
REF
is up to nominal level
BIT# BIT Function: Powerdown
8 PR0 1 = Powerdown ADCs and Record Select Mux
9 PR1 1 = Powerdown DACs
10 PR2 1 = Powerdown Analog Mixer (V
REF
still on)
11 PR3 1 = Powerdown Analog Mixer (V
REF
off)
12 PR4 1 = Powerdown AC Link digital interface (BIT_CLK off)
13 PR5 1 = Disable Internal Clock
14 PR6 1 = Powerdown Headphone Amplifier
External Amplifier PowerDown
15 EAPD
*0 = Set EAPD Pin to 0 (pin 47)
Default: 000Xh
EXTENDED AUDIO ID REGISTER (28h)
This read-only (X201h) register identifies which AC '97 Extended Audio features are supported. The LM4550
features AMAP (Slot/DAC mappings based on Codec Identity), VRA (Variable Rate Audio) and ID1, ID0, the
Codec Identity bits used to support multi-codec systems. AMAP is indicated by a "1" in bit 9, VRA is indicated by
a "1" in bit 0. The two MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#,
ID0#. Note that the external logic connections to ID1#, ID0# (pins 46 and 45) are inverse in polarity to the value
of the Codec Identity (ID1, ID0) held in bits D15, D14. The AMAP Slot/DAC mappings are given in Table 19 in
the Multiple Codec section. Codec mode selections are shown in the table below.
Pin 46 Pin 45 D15,28h D14,28h Codec Identity
(ID1#) (ID0#) (ID1) (ID0) Mode
NC/DV
DD
NC/DV
DD
0 0 Primary
NC/DV
DD
GND 0 1 Secondary 1
GND NC/DV
DD
1 0 Secondary 2
GND GND 1 1 Secondary 3
EXTENDED AUDIO STATUS/CONTROL REGISTER (2Ah)
This read/write register provides status and control of the variable sample rate capabilities in the LM4550. Setting
the LSB of this register to "1" enables Variable Rate Audio (VRA) mode and allows DAC and ADC sample rates
to be programmed via registers 2Ch and 32h respectively.
BIT Function
VRA *0 = VRA off (Frame-rate sampling)
1 = VRA on
Default: 0000h
SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)
These read/write registers are used to set the sample rate for the left and right channels of the DAC (PCM DAC
Rate, 2Ch) and the ADC (PCM ADC Rate, 32h). When Variable Rate Audio is enabled via bit 0 of the Extended
Audio Control/Status register (2Ah), the sample rates can be programmed, in 1 Hz increments, to be any value
from 4 kHz to 48 kHz. The value required is the hexadecimal representation of the desired sample rate, e.g.
8000
10
= 1F40h. Below is a list of the most common sample rates and the corresponding register (hex) values.
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