Datasheet

OBSOLETE
LM4550
SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013 www.ti.com
Table 17. Record Gain Register (1Ch)
Mute Gx3:Gx0 Function
0 1111 22.5dB gain
0 0000 0dB gain
1 XXXX *mute
Default: 8000h
GENERAL PURPOSE REGISTER (20h)
This register controls many miscellaneous functions implemented on the LM4550. The miscellaneous control bits
include POP which allows the DAC output to bypass the National 3D Sound circuitry, 3D which enables or
disables the National 3D Sound circuitry, MIX which selects the MONO_OUT source, MS which controls the
Microphone Selection mux and LPBK which connects the output of the stereo ADC to the input of the stereo
DAC. LPBK provides a mixed-mode analog – digital – analog loopback path between analog inputs and analog
outputs.
BIT Function
PCM Out Path: *0 = 3D allowed
POP
1 = 3D bypassed
National 3D Sound: *0 = off
3D
1 = on
Mono output select: *0 = Mix
MIX
1 = Mic
Mic select: *0 = MIC1
MS
1 = MIC2
ADC/DAC Loopback: *0 = No Loopback
LPBK
1 = Loopback
Default: 0000h
3D CONTROL REGISTER (22h)
This read-only (0101h) register indicates, in accordance with the AC '97 Rev 2.1 Specification, the fixed depth
and center characteristics of the National 3D Sound stereo enhancement.
POWERDOWN CONTROL / STATUS REGISTER (26h)
This read/write register is used both to monitor subsystem readiness and also to program the LM4550
powerdown states. The 4 LSBs indicate status and the 8 MSBs control powerdown.
The 4 LSBs of this register indicate the status of the 4 audio subsections of the codec: Reference voltage,
Analog mixers and amplifiers, DAC section, ADC section. When the "Codec Ready" indicator bit in the AC Link
Input Frame (SDATA_IN: slot 0, bit 15) is a "1", it indicates that the AC Link and AC '97 registers are in a fully
operational state and that control and status information can be transferred. It does not indicate that the codec is
ready to send or receive audio PCM data or to pass signals through the analog I/O and mixers. To determine
that readiness, the Controller must check that the 4 LSBs of this register are set to “1” indicating that the
appropriate audio subsections are ready.
The powerdown bits PR0 – PR6 control internal subsections of the codec. They are implemented in compliance
with AC '97 Rev 2.1 to support the standard device power management states D0 – D3 as defined in the ACPI
and PCI Bus Power Management specification.
PR0 controls the powerdown state of the ADC and associated sampling rate conversion circuitry. PR1 controls
powerdown for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits
(MIX1, MIX2, National 3D Sound, Mono Out, Line Out). PR3 powers down V
REF
in addition to all the same mixer
circuits as PR2. PR4 powers down the AC Link digital interface – see Figure 24 for signal powerdown timing.
PR5 disables internal clocks. PR6 powers down the Headphone amplifier. EAPD controls the External Amplifier
PowerDown bit.
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