Datasheet

OBSOLETE
LM4550
www.ti.com SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
Table 13. SLOT 1, INPUT FRAME (continued)
Bits Description Comment
0 = Controller should send valid data in Slot 3 of the next Output
Slot 3 Request bit
Frame.
11
(PCM Left Audio)
1 = Controller should not send Slot 3 data.
0 = Controller should send valid data in Slot 4 of the next Output
Slot 4 Request bit
Frame.
10
(PCM Right Audio)
1 = Controller should not send Slot 4 data.
9 Slot 5 Request bit Unused - set to "0" by LM4550
0 = Controller should send valid data in Slot 6 of the next Output
Slot 6 Request bit
Frame.
8
(PCM Center)
1 = Controller should not send Slot 6 data.
0 = Controller should send valid Slot 7 data in the next Output Frame.
Slot 7 Request bit
7
(PCM Left Surround)
1 = Controller should not send Slot 7 data.
0 = Controller should send valid data in Slot 8 of next Output Frame.
Slot 8 Request bit
6
(PCM Right Surround)
1 = Controller should not send Slot 8 data.
0 = Controller should send valid data in Slot 9 of next Output Frame.
Slot 9 Request bit
5
(PCM LFE)
1 = Controller should not send Slot 9 data.
4:2 Unused Slot Request bits Stuffed with "0"s by LM4550
1,0 Reserved Stuffed with "0"s by LM4550
SDATA_IN: Slot 2 – Status Data
This slot returns 16-bit status data read from a codec control/status register. The codec sends the data in the
frame following a read-request by the controller (bit 15, slot 1 of the Output Frame). If no read-request was made
in the previous frame the codec will stuff this slot with zeros.
Table 14. SLOT 2, INPUT FRAME
Bits Description Comment
Data read from a codec control/status register.
19:4 Status Data
Stuffed with “0”s if no read-request in previous frame.
3:0 Reserved Stuffed with "0"s by LM4550
SDATA_IN: Slot 3 – PCM Record Left Channel
This slot contains sampled data from the left channel of the stereo ADC. The signal to be digitized is selected
using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record
Gain amplifier to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2
LSBs are stuffed with zeros.
Table 15. SLOT 3, INPUT FRAME
Bits Description Comment
19:2 PCM Record Left Channel data 18-bit PCM audio sample from left ADC
1:0 Reserved Stuffed with "0"s by LM4550
SDATA_IN: Slot 4 – PCM Record Right Channel
This slot contains sampled data from the right channel of the stereo ADC. The signal to be digitized is selected
using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record
Gain amplifier to the ADC.
This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2
LSBs are stuffed with zeros.
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