Datasheet

BIT_CLK
SDATA_IN
SYNC
LM4550 samples
SYNC assertion
LM4550 outputs
first bit of SDATA_IN
End of previous
Audio Frame
Codec
Ready
Slot
(1)
Slot
(2)
BIT_CLK
SDATA_IN
SYNC
End of previous
Audio Frame
Codec
Ready
Slot
(1)
Slot
(4)
³0´ Bit 19 Bit 0
Bit 19
Slot 2
Bit 0
Slot 12
SLOTS 2 to 12SLOT 1
³0´
Tag bits: &RGHF5HDG\DQG6ORW³9DOLG´ELWV
Tag Phase
20.8 Ps
(48 kHz)
Data Phase
Status Address / Slot
Request bits for VSA
Slot (x) = ³1´LQGLFDWHVWLPHVORWx contains valid PCM data
Data: Status and Audio
OBSOLETE
LM4550
www.ti.com SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
SDATA_OUT: Slots 5, 10, 11, 12 – Reserved
These slots are not used by the LM4550 and should all be stuffed with zeros by the AC '97 Controller.
Figure 22. AC Link Input Frame
AC LINK INPUT FRAME:
SDATA_IN, CONTROLLER INPUT FROM LM4550 OUTPUT
The AC Link Input Frame contains status and PCM data from the LM4550 control registers and stereo ADC.
Input Frames are carried on the SDATA_IN signal which is an input to the AC '97 Digital Audio Controller and an
output from the LM4550 codec. As shown in Figure 19, Input Frames are constructed from thirteen time slots:
one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by the
LM4550. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate the
validity of the data in the four of the twelve following Data Slots that are used by the LM4550. Each Frame
consists of 256 bits with each of the twelve data slots containing 20 bits.
A new Input Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller
on a rising edge of BIT_CLK and, as shown in Figure 22 and Figure 23, the first tag bit in the Frame (“Codec
Ready”) is clocked from the LM4550 by the next rising edge of BIT_CLK. The LM4550 always clocks data to
SDATA_IN on a rising edge of BIT_CLK and the controller is expected to sample SDATA_IN on the next falling
edge. The LM4550 samples SYNC on the rising edge of BIT_CLK.
Input and Output Frames are aligned to the same SYNC transition.
The LM4550 checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high
transition on SYNC) before 256 bits are received from an old Frame then the new Frame is ignored i.e. no valid
data is sent on SDATA_IN until a valid new Frame is detected.
The LM4550 transmits data MSB first, in an MSB justified format. All reserved bits and slots are stuffed with "0"s
by the LM4550.
Figure 23. Start of AC Link Input Frame
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