Datasheet

BIT_CLK
SDATA_OUT
SYNC
LM4550 samples
SYNC assertion
LM4550 samples
first bit of SDATA_OUT
End of previous
Audio Frame
Valid
Frame
Slot
(1)
Slot
(2)
OBSOLETE
LM4550
www.ti.com SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
Figure 21. Start of AC Link Output Frame
Table 6. SLOT 0, OUTPUT FRAME
Bit Description Comment
15 Valid Frame 1 = Valid data in at least one slot.
14 Control register address 1 = Valid Control Address in Slot 1 (Primary codec only)
13 Control register data 1 = Valid Control Data in Slot 2 (Primary codec only)
1 = Valid PCM Data in Slot 3
12 Left DAC data in Slot 3
(Primary & Secondary 1 modes; Left Channel audio)
1 = Valid PCM Data in Slot 4
11 Right DAC data in Slot 4
(Primary & Secondary 1 modes; Right Channel audio)
10 Not Used Controller should stuff this slot with “0”s
1 = Valid PCM Data in Slot 6
9 Left DAC data in Slot 6
(Secondary 3 mode; Center Channel audio)
1 = Valid PCM Data in Slot 7
8 Left DAC data in Slot 7
(Secondary 2 mode; Left Surround Channel audio)
1 = Valid PCM Data in Slot 8
7 Right DAC data in Slot 8
(Secondary 2 mode; Right Surround Channel audio)
1 = Valid PCM Data in Slot 9
6 Right DAC data in Slot 9
(Secondary 3 mode; LFE Channel audio)
5:2 Not Used Controller should stuff these slots with “0”s
Codec ID The Codec ID (Table 19) selects the target codec in a multi-codec system to
1,0
(ID1, ID0) receive the control address and data carried in the Output Frame
SDATA_OUT: Slot 1 – Read/Write, Control Address
Slot 1 is used by a controller to indicate both the address of a target register in the LM4550 and whether the
access operation is a register read or register write. The MSB of slot 1 (bit 19) is set to 1 to indicate that the
current access operation is 'read'. Bits 18 through 12 are used to specify the 7-bit register address of the read or
write operation. The least significant twelve bits are reserved and should be stuffed with zeros by the AC '97
controller.
Table 7. SLOT 1, OUTPUT FRAME
Bits Description Comment
1 = Read
19 Read/Write
0 = Write
18:12 Register Address Identifies the Status/Command register for read/write
11:0 Reserved Controller should set to "0"
SDATA_OUT: Slot 2 – Control Data
Slot 2 is used to transmit 16-bit control data to the LM4550 when the access operation is 'write'. The least
significant four bits should be stuffed with zeros by the AC '97 controller. If the access operation is a register
read, the entire slot, bits 19 through 0 should be stuffed with zeros.
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