Datasheet

OBSOLETE
LM4550
www.ti.com SNAS032F –SEPTEMBER 2001–REVISED APRIL 2013
Table 2. DIGITAL I/O AND CLOCKING (continued)
Name Pin I / O Functional Description
Output from codec
This is the output for AC Link Input Frames from the LM4550 codec to an AC '97 Digital Audio
SDATA_IN 8 O
Controller. These frames can contain both codec status data and PCM audio data from the ADCs. The
LM4550 clocks data from this output on the rising edge of BIT_CLK.
AC Link frame marker and Warm Reset
This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In
normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is
sampled on the rising edge of BIT_CLK and the codec takes the first positive sample of SYNC as
SYNC 10 I
defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLK
periods of the frame start it will be ignored.
SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset is
used to clear a power down state on the codec AC Link interface.
Cold Reset
This active low signal causes a hardware reset which returns the control registers and all internal
circuits to their default conditions. RESET# must be used to initialize the LM4550 after Power On
RESET# 11 I
when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor test
modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels of the
LINE_OUT stereo output.
Codec Identity
ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures the
codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted
polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID
ID0# 45 I
register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit (D14, reg 28h) will be set
to “1”. Similarly, connection to DV
DD
will set the ID0 bit to “0”. If left open (NC), ID0# is pulled high by
an internal pull-up resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h.
See the register description and the CIN pin description for details.
Codec Identity
ID1# and ID0# determine the codec address for multiple codec use. The Codec Identity configures the
codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted
polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID
ID1# 46 I
register, 28h. If the ID1# pin (pin 46) is connected to ground then the ID1 bit (D15, reg 28h) will be set
to “1”. Similarly, connection to DV
DD
will set the ID1 bit to “0”. If left open (NC), ID1# is pulled high by
an internal pull-up resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h.
See the register description and the CIN pin description for details.
External Amplifier Power Down control signal
This output is set by the EAPD bit (bit D15) in the Powerdown Control/Status register, 26h. As with the
EAPD 47 O other logic outputs, the output voltage is set by DV
DD
. This pin is intended to be connected to the
shutdown pin on an external power amplifier. For normal operation the default value of EAPD=0 will
enable the external amplifier allowing an input on PC_BEEP to be heard during Cold Reset.
Chain In
The codec can be instructed to disconnect its own SDATA_IN signal and instead pass the signal on
CIN through to the SDATA_IN output pin. This is achieved by changing the value of the two LSBs of
the Chain-In Control register (74h) so that they differ from the Codec Identity bits ID1, ID0. Those two
LSBs default to the value of the Codec Identity bits following Cold Reset thereby disabling the Chain In
CIN 48 I feature. Chain In can also be disabled by reading the Codec Identity from the Extended Audio ID
register (28h) and writing the value back into register 74h LSBs. The Codec Identity bits are
determined by the input pins ID1#, ID0#.
CIN can be left open (NC) provided that the chain feature is disabled. When the chain feature is used,
CIN should always be driven. Either connect the SDATA_IN pin from another codec or else ground
CIN to prevent the possibility of floating the SDATA_IN signal at the controller.
Table 3. POWER SUPPLIES AND REFERENCES
Name Pin I / O Functional Description
AV
DD
25 I Analog supply
AV
SS
26 I Analog ground
DV
DD1
1 I Digital supply
DV
DD2
9 I Digital supply
DV
SS1
4 I Digital ground
DV
SS2
7 I Digital ground
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