Datasheet
LM4549B
www.ti.com
SNAS598A –JULY 2012–REVISED MAY 2013
Electrical Characteristics
(1)(2)
(continued)
The following specifications apply for AV
DD
= 5V, DV
DD
= 3.3V, Fs = 48 kHz, single codec configuration, (primary mode)
unless otherwise noted. Limits apply for T
A
= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.
LM4549B
Units
Symbol Parameter Conditions
Typical Limit
(Limits)
(3) (4)
0.65 x
V
IH
High level input voltage V (min)
DV
DD
0.35 x
V
IL
Low level input voltage V (max)
DV
DD
0.90 x
V
OH
High level output voltage I
O
= −2.5 mA. V (min)
DV
DD
0.10 x
V
OL
Low level output voltage I
O
= 2.5 mA. V (max)
DV
DD
I
L
Input Leakage Current AC Link inputs ±10 µA
I
L
Tri state Leakage Current High impedance AC Link outputs ±10 µA
C
IN
AC-Link I/O capacitance
(7)
SDout, BitClk, SDin, Sync, Reset# only 4 7.5 pF (max)
I
DR
Output drive current AC Link outputs 5 mA
Digital Timing Specifications
(7)
F
BC
BIT_CLK frequency 12.288 MHz
T
BCP
BIT_CLK period 81.4 ns
T
CH
BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20 % (max)
F
SYNC
SYNC frequency 48 kHz
T
SP
SYNC period 20.8 µs
T
SH
SYNC high pulse width 1.3 µs
T
SL
SYNC low pulse width 19.5 µs
T
DSETUP
Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 3.5 10 ns (min)
Hold time of SDATA_OUT from falling edge
T
DHOLD
Hold Time for codec data input
(9)
5.3 10 ns (min)
of BIT_CLK
T
SSETUP
Setup Time for codec SYNC input
(9)
SYNC to falling edge of BIT_CLK 3.8 10 ns (min)
Hold time of SYNC from falling edge of
T
SHOLD
Hold Time for codec SYNC inpu
(9)
t 10 ns (min)
BIT_CLK
Output Delay of SDATA_IN from rising
T
CO
Output Valid Delay 5.2 15 ns (max)
edge of BIT_CLK
BIT_CLK, SYNC, SDATA_IN or
T
RISE
Rise Time
(9)
6 ns (max)
SDATA_OUT
BIT_CLK, SYNC, SDATA_IN or
T
FALL
Fall Time
(9)
6 ns (max)
SDATA_OUT
T
RST_LOW
RESET# active low pulse width
(9)
For Cold Reset 1.0 µs (min)
T
RST2CLK
RESET# inactive to BIT_CLK start up For Cold Reset 271 162.8 ns (min)
T
SH
SYNC active high pulse width
(9)
For Warm Reset 1.0 µs (min)
T
SYNC2CLK
SYNC inactive to BIT_CLK start up For Warm Reset 162.8 ns (min)
Delay from end of Slot 2 to BIT_CLK,
T
S2_PDOWN
AC Link Power Down Delay 1 µs (max)
SDATA_IN low
Time from minimum valid supply levels to
T
SUPPLY2RST
Power On Reset 1 µs (min)
end of Reset
T
SU2RST
Setup to trailing edge of RESET#
(9)
For ATE Test Mode 15 ns (min)
T
RST2HZ
Rising edge of RESET# to Hi-Z
(9)
For ATE Test Mode 25 ns (max)
(9) These specifications are ensured by design and characterization; they are not production tested.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM4549B