Datasheet

$&¶97 SECONDARY 2
ID = 10
[97 SECONDARY 1
DOCKING: ID = 01
$&¶97 SECONDARY 3
ID = 11
[97 PRIMARY
MASTER: ID = 00
SDATA_IN1
SDATA_IN2
SYNC
SDATA_IN0
RESET#
SDATA_OUT
BIT_CLK
ID1#
ID0#
SYNC
SDATA_IN
RESET#
SDATA_OUT
BIT_CLK
45
46
Slots 3 & 4
Line_Out_L
Line_Out_R
DV
DD
/NC
DV
DD
/NC
ID1#
ID0#
SYNC
SDATA_IN
RESET#
SDATA_OUT
BIT_CLK
45
46
Slots 3 & 4
Line_Out_L
Line_Out_R
DV
DD
/NC
ID1#
ID0#
SYNC
SDATA_IN
RESET#
SDATA_OUT
BIT_CLK
45
46
Slots 3 & 4
DV
DD
/NC
ID1#
ID0#
SYNC
SDATA_IN
RESET#
SDATA_OUT
BIT_CLK
45
46
Slots 3 & 4
Line_Out_L
Line_Out_R
[97
DIGITAL CONTROLLER
SDATA_IN3
Line_Out_L
Line_Out_R
XTAL_IN
XTAL_OUT
LM4549B
SNAS598A –JULY 2012–REVISED MAY 2013 www.ti.com
Figure 23. Multiple Codecs using Extended AC Link
Test Modes
AC '97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit
either of them. The ATE test mode is activated if SDATA_OUT is sampled high by the trailing edge (zero-to-one
transition) of RESET#. In ATE test mode the codec AC Link outputs SDATA_IN and BIT_CLK are configured to a
high impedance state to allow tester control of the AC Link interface for controller testing. ATE test mode timing
parameters are given in the Electrical Characteristics table. The Vendor test mode is entered if SYNC is sampled
high by the zero-to-one transition of RESET#. Neither of these entry conditions can occur in normal AC Link
operation but care must be taken to avoid mistaken activation of the test modes when using non standard
controllers.
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