Datasheet

LM4549B
www.ti.com
SNAS598A JULY 2012REVISED MAY 2013
When reading from a Secondary Codec, the controller must send the correct Codec ID bits (i.e. the target Codec
Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) and target register address (slot 1,
bits 18 12). To write to a Secondary Codec, a controller must send the correct Codec ID bits when slot 1
contains a valid target register address and “write” indicator bit and slot 2 contains valid target register data. A
write operation is only valid if the register address and data are both valid and sent within the same frame. When
accessing the Primary Codec, the Codec ID bits are cleared and the tag bits 14 and 13 resume their role
indicating the validity of Command Address and Data in slots 1 and 2.
The use of the tag bits in Input Frames (carried by the SDATA_IN signal) is the same for Primary and Secondary
Codecs.
The Codec Identity is determined by the inverting input pins ID1#, ID0# (pins 46 and 45) and can be read as the
value of the ID1, ID0 bits (D15, D14) in the Extended Audio ID register, 28h of the target codec.
Slots in the AC Link Output Frame are always mapped to carry data to the left DAC channel in slot 3 and data to
the right DAC channel in slot 4. Similarly, slots in AC Link Input Frames are always mapped such that PCM data
from the left ADC channel is carried by slot 3 and PCM data from the right ADC channel by slot 4. Output
Frames are those carried by the SDATA_OUT signal from the controller to the codec while Input Frames are
those carried by the SDATA_IN signal from the codec to the controller.
Slot 0: TAG bits in Output Frames (controller to codec)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Valid Slot 1 Slot 2 Slot 3 Slot 4
X X X X X X X X X ID1 ID0
Frame Valid Valid Valid Valid
Extended Audio ID register (28h): Support for Multiple Codecs
Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
Extended
28h ID1 ID0 X X X X X X X X X X X X X VRA X001h
Audio ID
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