Datasheet

LM4549B
SNAS598A –JULY 2012–REVISED MAY 2013 www.ti.com
The bandgap reference and the anti-pop slow turn-on circuit were improved in the LM4549B. A pullup resistor is
not required on V
REF
, pin 27. For an existing design, the 10 kΩ resistor can be left on the pc board, but the
temperature coefficient will improve with no resistor on this pin. In addition, the THD will improve by 0.2–0.5 dB.
The external capacitor is charged by an internal current source, ramping the voltage slowly. This results in slow
turn-on of the audio stages, eliminating “pops and clicks”. Thus, turn-on performance is also improved. The
pullup resistor, in conjunction with the internal impedance and the external capacitor, form a frequency
dependent divider from the analog supply. Noise on the analog supply will be coupled into the audio path, with
approximately 30 dB. of attenuation. Although this is not a large amount if the noise on the supply is tens of
millivolts, it will prevent SNR from exceeding 80 dB.
In Figure 8 and Figure 9, the input coupling capacitors are shown as 1 µF capacitors. This is only necessary for
extending the response down to 20 Hz. for music applications. For telematics or voice applications, thelower 3
dB. point can be much higher. Using a specified input resistance of 10 kΩ, (40 kΩ typical), a 0.1 µF capacitor
may be used. The lower 3 dB point will still be below 300 Hz. By using a smaller capacitor, the package size may
be reduced, leading to a lower system cost.
Backwards Compatibility
The LM4549B is improved compared with the LM4549A. If it is required to build a board that will use either part,
a 10 kΩ resistor must be added from the V
REF
pin (pin 27) to AV
DD
for the LM4549A. It is not required for the
LM4549B. Addition of this resistor will slightly increase the temperature coefficient of the internal bandgap
reference and decrease the THD performance, but overall performance will still be better than the LM4549A. The
LM4549A requires that pins 1 and 9 (DV
DD
) connect directly to a 27 nH. inductor before going to the 3.3 Volt
digital supply and the bypass capacitors. The inductor is not required for the LM4549B and should not be used.
Multiple Codecs
Extended AC Link
Up to four codecs can be supported on the extended AC Link. These multiple codec implementations should run
off a common BIT_CLK generated by the Primary Codec. All codecs share the AC '97 Digital Controller output
signals, SYNC, SDATA_OUT, and RESET#. Each codec, however, supplies its own SDATA_IN signal back to
the controller, with the result that the controller requires one dedicated input pin per codec. (Figure 23).
By definition there can be one Primary Codec and up to three Secondary Codecs on an extended AC Link. The
Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00 while Secondary Codecs may have identities equal to
01, 10 or 11. The Codec Identity is used as a chip select function. This allows the Command and Status registers
in any of the codecs to be individually addressed although the access mechanism for Secondary Codecs differs
slightly from that for a Primary.
The Identity control pins, ID1#, ID0# (pins 46 and 45) are internally pulled up to DV
DD
. The Codec may therefore
be configured as 'Primary' either by leaving ID1#, ID0# open (NC) or by strapping them externally to DV
DD
(Digital Supply).
The difference between Primary and Secondary codec modes is in their timing source and in the Tag Bit
handling in Output Frames for Command/Status register access. For a timing source, a Primary codec divides
down by 2 the frequency of the signal on XTAL_IN and also generates this as the BIT_CLK output for the use of
the controller and any Secondary codecs. Secondary codecs use BIT_CLK as an input and as their timing source
and do not use XTAL_IN or XTAL_OUT. The use of Tag Bits is described below.
Secondary Codec Register Access
For Secondary Codec access, the controller must set the tag bits for Command Address and Data in the Output
Frame as invalid (i.e. equal to 0). The Command Address and Data tag bits are in slot 0, bits 14 and 13 and
Output Frames are those in the SDATA_OUT signal from controller to codec. The controller must also place the
non-zero value (01, 10, or 11) corresponding to the Identity (ID1, ID0) of the target Secondary Codec into the
Codec ID field (slot 0, bits 1 and 0) in that same Output Frame. The value set in the Codec ID field determines
which of the three possible Secondary Codecs is accessed. Unlike a Primary Codec, a Secondary Codec will
disregard the Command Address and Data tag bits when there is a match between the 2-bit Codec ID value (slot
0, bits 1 and 0) and the Codec Identity (ID1, ID0). Instead it uses the Codec-ID/Identity match to indicate that the
Command Address in slot 1 and (if a “write”) the Command Data in slot 2 are valid.
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