Datasheet
LM4549B
SNAS598A –JULY 2012–REVISED MAY 2013
www.ti.com
Pin 46 Pin 45 D15,28h D14,28h Codec Identity
(ID1#) (ID0#) (ID1) (ID0) Mode
NC/DV
DD
NC/DV
DD
0 0 Primary
NC/DV
DD
GND 0 1 Secondary 1
GND NC/DV
DD
1 0 Secondary 2
GND GND 1 1 Secondary 3
Extended Audio Status/Control register (2Ah)
This read/write register provides status and control of the variable sample rate capabilities in the LM4549B.
Setting the LSB of this register to "1" enables Variable Rate Audio (VRA) mode and allows DAC and ADC
sample rates to be programmed via registers 2Ch and 32h respectively.
BIT Function
VRA *0 = VRA off (Frame-rate sampling)
1 = VRA on
Default: 0000h
Sample Rate Control Registers (2Ch, 32h)
These read/write registers are used to set the sample rate for the left and right channels of the DAC (PCM DAC
Rate, 2Ch) and the ADC (PCM ADC Rate, 32h). When Variable Rate Audio is enabled via bit 0 of the Extended
Audio Control/Status register (2Ah), the sample rates can be programmed, in 1 Hz increments, to be any value
from 4 kHz to 48 kHz. The value required is the hexadecimal representation of the desired sample rate, e.g.
8000
10
= 1F40h. Below is a list of the most common sample rates and the corresponding register (hex) values.
Table 11. Common Sample Rates
SR15:SR0 Sample Rate (Hz)
1F40h 8000
2B11h 11025
3E80h 16000
5622h 22050
AC44h 44100
*BB80h *48000
Vendor ID Registers (7Ch, 7Eh)
These two read-only (4E53h, 4349h) registers contain TI's Vendor ID and TI's LM45xx codec version
designation. The first 24 bits (4Eh, 53h, 43h) represent the three ASCII characters “NSC” which is TI's Vendor ID
for Microsoft's Plug and Play. The last 8 bits are the two binary coded decimal characters, 4, 9 and identify the
codec to be an LM4549B.
Reserved Registers
Do not write to reserved registers. In particular, do not write to registers 24h, 5Ah, 74h and 7Ah. All registers not
listed in the LM4549B Register Map are reserved. Reserved registers will return 0000h if read.
Low Power Modes
The LM4549B provides 6 bits to control the powerdown state of internal analog and digital subsections and
clocks. It also provides one bit intended to control an external analog power amplifier. These 7 bits (PR0 – PR5,
EAPD) are located in the 8 MSBs of the Powerdown Control/Status register, 26h. The status of the four main
analog subsections is given by the 4 LSBs in the same register, 26h.
The powerdown bits are implemented in compliance with AC '97 Rev 2.1 to support the standard device power
management states D0 – D3 as defined in the ACPI and PCI Bus Power Management Specification.
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