Datasheet

LM4549B
www.ti.com SNAS598A –JULY 2012–REVISED MAY 2013
3D Control Register (22h)
This read-only (0101h) register indicates, in accordance with the AC '97 Rev 2.1 Specification, the fixed depth
and center characteristics of the TI 3D Sound stereo enhancement.
Powerdown Control / Status Register (26h)
This read/write register is used both to monitor subsystem readiness and also to program the LM4549B
powerdown states. The 4 LSBs indicate status and 7 of the 8 MSBs control powerdown.
The 4 LSBs of this register indicate the status of the 4 audio subsections of the codec: Reference voltage,
Analog mixers and amplifiers, DAC section, ADC section. When the "Codec Ready" indicator bit in the AC Link
Input Frame (SDATA_IN: slot 0, bit 15) is a "1", it indicates that the AC Link and AC '97 registers are in a fully
operational state and that control and status information can be transferred. It does NOT indicate that the codec
is ready to send or receive audio PCM data or to pass signals through the analog I/O and mixers. To determine
that readiness, the Controller must check that the 4 LSBs of this register are set to “1” indicating that the
appropriate audio subsections are ready.
The powerdown bits PR0 – PR5 control internal subsections of the codec. They are implemented in compliance
with AC '97 Rev 2.1 to support the standard device power management states D0 – D3 as defined in the ACPI
and PCI Bus Power Management Specification.
PR0 controls the powerdown state of the ADC and associated sampling rate conversion circuitry. PR1 controls
powerdown for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits
(MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down V
REF
in addition to all the same mixer
circuits as PR2. PR4 powers down the AC Link digital interface – see Figure 22 for signal powerdown timing.
PR5 disables internal clocks. PR6 is not used. EAPD controls the External Amplifier PowerDown bit.
BIT# BIT Function: Status
0 ADC 1 = ADC section ready to transmit data
1 DAC 1 = DAC section ready to accept data
2 ANL 1 = Analog mixers ready
3 REF 1 = V
REF
is up to nominal level
BIT# BIT Function: Powerdown
8 PR0 1 = Powerdown ADCs and Record Select Mux
9 PR1 1 = Powerdown DACs
10 PR2 1 = Powerdown Analog Mixer (V
REF
still on)
11 PR3 1 = Powerdown Analog Mixer (V
REF
off)
12 PR4 1 = Powerdown AC Link digital interface (BIT_CLK off)
13 PR5 1 = Disable Internal Clock
14 PR6 Not Used
External Amplifier PowerDown
15 EAPD
*0 = Set EAPD Pin to 0 (pin 47)
Default: 000Fh If ready;
otherwise 000Xh
Extended Audio ID Register (28h)
This read-only (X001h) register identifies which AC '97 Extended Audio features are supported. The LM4549B
features VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec support). VRA is indicated by a "1" in bit 0. The
two MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#, ID0#. Note that the
external logic connections to ID1#, ID0# (pins 46 and 45) are inverse in polarity to the value of the Codec Identity
(ID1, ID0) held in bits D15, D14. Codec mode selections are shown in the table below.
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