Datasheet

LM4549B

SNAS598A –JULY 2012–REVISED MAY 2013

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This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2

LSBs are stuffed with zeros.

Table 9. Slot 4, Input Frame

Bits Description Comment

19:2 PCM Record Right Channel data 18-bit PCM sample from right ADC

1:0 Reserved Stuffed with "0"s by LM4549B

SDATA_IN: Slots 5 to 12 – Reserved

Slots 5 – 12 of the AC Link Input Frame are not used for data by the LM4549B and are always stuffed with

zeros.

Default settings are indicated by *.

Reset Register (00h)

Writing any value to this register causes a Register Reset which changes all registers back to their default

values. If a read is performed on this register, the LM4549B will return a value of 0D40h. This value can be

interpreted in accordance with the AC '97 Specification to indicate that TI 3D Sound is implemented and 18-bit

data is supported for both the ADCs and DACs.

Master Volume Register (02h)

This output register allows the output level from either channel of the stereo LINE_OUT to be muted or

attenuated over the range 0 dB – 46.5 dB in nominal 1.5 dB steps. There are 6 bits of volume control for each

channel and both stereo channels can be individually attenuated. The mute bit (D15) acts simultaneously on both

stereo channels of LINE_OUT. The AC'97 specification states that “support for the MSB of the level is optional.”

All six bits may be written to the register, but if the MSB is a '1', the MSB is ignored and the register will be set to

0 11111. This will be the value when the register is read, allowing the software driver to detect whether the MSB

is supported or not.

Mute Mx5:Mx0 Function

0 0 00000 0 dB attenuation

0 0 11111 46.5 dB attenuation

0 1 xxxxx As Written

0 0 11111 As read back

1 X XXXXX *mute

Default: 8000h

Line Level Volume Register (04h)

This output register allows the level from both channels of LNLVL_OUT to be muted or individually attenuated

over the range 0 dB to –46.5 dB in nominal 1.5 dB steps. There are 6 bits of volume control for each channel

plus one mute bit. The mute bit (D15) acts on both channels. Operation of this register and LNLVL_OUT

matches that of the Master Volume register and the LINE_OUT output.

Mono Volume Register (06h)

This output register allows the level from MONO_OUT to be muted or attenuated over the range 0 dB – 46.5 dB

in nominal 1.5 dB steps. There are 6 bits of volume control and one mute bit (D15). All six bits may be written to

the register, but if the MSB is a 1, the MSB is ignored and the register will be set to 0 11111. This will be the

value when the register is read, allowing the software driver to detect whether the MSB is supported or not.

Product Folder Links: LM4549B